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Gate Mock Test: Electrical Engineering(EE)- 2


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65 Questions MCQ Test GATE Electrical Engineering (EE) 2023 Mock Test Series | Gate Mock Test: Electrical Engineering(EE)- 2

Gate Mock Test: Electrical Engineering(EE)- 2 for GATE 2022 is part of GATE Electrical Engineering (EE) 2023 Mock Test Series preparation. The Gate Mock Test: Electrical Engineering(EE)- 2 questions and answers have been prepared according to the GATE exam syllabus.The Gate Mock Test: Electrical Engineering(EE)- 2 MCQs are made for GATE 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Gate Mock Test: Electrical Engineering(EE)- 2 below.
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Gate Mock Test: Electrical Engineering(EE)- 2 - Question 1

A number of Indian goods face a _____ competition from Chinese goods in terms of prices and looks.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 1 The sentence implies that a powerful competition is faced by Indian goods from Chinese goods. ‘Fierce’ meaning ‘powerful and destructive’ is the apt fit for the blank.

Hence, option C is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 2

In the following question, out of the five alternatives, select the word similar in meaning to the given word.

Appease

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 2 Appease = to bring to a state of peace, quiet, ease, calm, or contentment; pacify; soothe.

Agitate = make (someone) troubled or nervous.

Pacify = to cause someone who is angry or upset to be calm and satisfied.

Interrupt = stop the continuous progress of (an activity or process).

So, option B is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 3

Select the most appropriate option to substitute the underlined segment in the given sentence. If there is no need to substitute it, select No improvement.

It is not wise relying to anybody too much.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 3 ‘Rely on’ is the phrase which means to be dependent as for support or maintenance. All other choices fail to provide the correct meaning to the sentence both contextually as well as grammatically.

Therefore, we can say option C is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 4

Select the most appropriate option to substitute the underlined segment in the given sentence. If no substitution is required, select No improvement.

His miserable condition made us wept.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 4 The English verbs let, make, have, Get, and Help are called causative verbs

because they cause something else to happen. The grammatical structure for make is given below:

MAKE + PERSON + VERB (base form).

The structure given in option A follows the above rule.

So, it is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 5

Select the most appropriate word to fill in the blank.

Many items made of ivory were _____ from a dealer in antiques by the custom authorities at the Delhi airport.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 5 The sentence implies that the custom authorities seized many items made of ivory.

‘Confiscate’ means ‘take or seize (someone's property) with authority’. This word fits best in the sentence.

Therefore, option A is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 6

Select the most appropriate option to substitute the underlined segment in the given sentence. If there is no need to substitute it, select No improvement

The man who seen the accident to occur telephoned the police.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 6 The sentence shows two actions occurring in past with a considerable gap between them. The act of the man seeing the occurrence of the accident happened first and then the man telephoned the police. In such situations, we need to keep the first occurring action in past perfect tense and second event will be kept in simple past tense.

Therefore, option B is the correct response.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 7

Select the most appropriate option to substitute the underlined segment in the given sentence. If no substitution is required, select No improvement.

If you listen to English news, it improve your English.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 7 The given sentence is an example of first conditional sentences. The first conditional is a structure we use when we want to talk about possibilities in the present or in the future. The first conditional has simple present after 'if' or ‘when’, then the simple future in the other clause.

Hence, option B is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 8

Select the most appropriate word to fill in the blank.

Scientists at Cambridge University are ______ how plants can give us sustainable energy.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 8

The sentence implies that the scientists at Cambridge University are carrying out the research to find how plants can give us sustainable energy.

‘Investigating’ meaning ‘carry out research or study into (a subject or problem, typically one in a scientific or academic field)’ perfectly fits in the blank.

Hence, option B is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 9

In the following question, out of the five alternatives, select the word similar in meaning to the given word.

Acrimonious

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 9

Acrimonious (adj.): (typically of speech or discussion) angry and bitter.

Tawdry (adj.): showy but cheap and of poor quality.

Gaudy (adj.): extravagantly bright or showy, typically so as to be tasteless.

Vitriolic (adj.): violent hate and anger expressed through severe criticism.

Ameliorate (v.):

make (something bad or unsatisfactory) better.

Courteous (adj.): polite, respectful, or considerate in manner.

So, the correct answer is option B.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 10

Direction: In the following question, a part of the sentence is bold. Below the sentence alternatives to the bold part are given at (A), (B) and (C) which may improve the sentence. Choose the correct alternative. In case ‘No improvement’ is needed, your answer is (D).

The professor has agreed to take remediable classes for the weaker students.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 10

'Remedial' should be used to make the sentence grammatically correct. It means giving or intended as a remedy or cure while remediable means capable of being cured; treatable. The classes don't need to be cured.

Thus, option B is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 11

The open loop transfer function of a unity negative feedback system is given by Find the value of 'K' such that the phase margin is 60

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 11

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 12

The starting current of a star-connected, 3-phase induction motor at rated voltage is 6 times the full load current and full load slip of 5%. Auto-transformer is used to limit the starting current from mains to 4 times the full load current. Determine the ratio of starting torque to the full load torque.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 12 In case of auto transformer,

As we known

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 13

A DC voltage of 50 V is applied to a coil having R = 10 Ω, L = 10 H. The time taken by the current to reach 75% of its final value is –

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 13 In a coil having R and L.

The charging current will be

i = 1 (1 - e - t/T)

i = 5 [ l - e-7]

Time required to reach 75% of its final value,

0.75 x 5 = 5 [1 - e-]

e-t = 0.25

t = 1.386 sec

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 14

For the operational amplifier circuit shown in the figure below, what is the maximum possible value of R1, if the voltage gain required is between – 10 and – 25? (The upper limit on RF is 1 MΩ)

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 14

So lesser the gain higher will be R1

So fo r AV = - 10

→ R1 will be maximum

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 15

In the circuit of figure, Vs = 2 cos3t volts the VL(t) will be-

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 15 Current across capacitor

Where,

V0 = [2 cos 3f] volts

Voltage across inductor

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 16

The power absorbed by 0.5 Ω resistance in the given circuit is:

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 16 The circuit can be redrawn as

Since, bridge is in the balanced condition.

So, power absorbed by 0.5Ω resistance is

P = 12R = ((3.43)2 × 0.5) = 5.88W

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 17

In a 132 kV system, the series inductance up to the point of circuit breaker location is 50 mH. The shunt capacitance at the circuit breaker terminal is 0.05 μF. The critical value of resistance in ohms required to be connected across the circuit breaker contacts which will give no transient oscillation is _____________.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 17 Given data L = 50 mH, C = 0.05 μF

Critical resistance to have transient free oscillations is

R = 500 Ω

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 18

A signal x(t) is denoted by a function which is periodic and continuous in its time domain representation. Then, which of the following would be true for the fourier transform of the signal

(i) Discrete and Periodic

(ii) Discrete and Aperiodic

(iii) Real{x(t)} transforms in to Real{X(jω)}

(iv) Real{x(t)} transforms in to Imag{X(jω)}

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 18 It is a well-established thumb rule that is tabulated below

Also, Even part of a signal gets transformed into real part of Fourier representation and Odd part of signal gets transformed into Imaginary part of Fourier representation.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 19

Find the differential equation of the system described by the transfer function given as:

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 19 We have,

⇒ Y (s) [2s2 + 5s] = X(s) • (s + 3)

⇒ 2s2 • y(s) + 5 • y(s) = s • X(s) + 3. X(s)

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 20

Which of the following is correct for 1110100 ÷ 1010?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 20 By simple divide method,

1010) 1110100(1011

(1) 1) 1) 1) 1) 1) 1010

10000

1010

110

Therefore, Quotient= 1011 and remainder= 110

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 21

Fault current of a line to ground fault and LLL fault for an unloaded generator is same. If X1 =0.3 pu, X2 = 0.2 pu and Xo = 0.04 pu. Then calculate value of inductive reactance (Xn) required for natural grounding (in pu)


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 21

for LG fault:-

IfLG = 3 ER1 / (X1 eq + X 2eq + X oeq)

For LLL fault:-

ILL = E R1 / X 1eq

ILL = 1/0.3

Both faults currents are same

IFLG = LFLL

0 .54 + 3 X n = 0 .9

3 Xn = 0.9 - 0.54

Grounding reactance (Xn) = 0.12 pu

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 22

Determine the value of V and I in the given network.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 22 Applying nodal analysis,

⇒ 2V + 4(V - 6) + V = 0

⇒ 2V + 4V - 24 + V = 0

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 23

The instantaneous polarity of primary winding of an ideal transformer is shown in figure below. The direction of flux and polarity of instantaneous voltage induced in secondary is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 23 For the given direction of current and polarity of induced voltage in primary, according to principle of Right Hand Thumb Rule the direction of flux will be clockwise and as the instantaneous direction of flux is clockwise, according to Lenz's law as effect opposes cause, the polarity of instantaneous induced in secondary is 'd' negative and 'c positive'.
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 24

Given below is a 3-phase full-bridge rectifier. When the diode D3 is conducting, which of the following diodes cannot conduct at the same time?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 24 KVL around any path shows that only one diode in the top half of the bridge will conduct at the same time. The diode that is conducting has its anode connected to the highest phase voltage at that moment. Hence, when

D3 is conducting, D1 and D5 cannot conduct. Similarly, only one diode can conduct in the bottom half at the same time. The diode that is conducting has its cathode connected to the lowest phase voltage at that moment. Hence, when D3 is conducting, D6 cannot conduct.

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 25

A simple slide wire potentiometer is used for measurement of current in a circuit. The voltage drop across a standard resistor of 0.5 Ω is balanced at 95 cm. find the magnitude of the current (in Ampere) if the standard cell emf of 1.95 volts is balanced at 60 cm.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 25 The answer is in between 6.5 and 7

For the same working current, if 60 cm corresponds to 1.95 volt.

Then 95cm of the slide wire corresponds to =1.95 / 60x10-2 x 95x10-2 = 3.421 volt

So, cross the resistance 0.5 Ω the voltage drop is 3.421 volt.

Then the value of the current is (I) = 3.421 / 0.5 = 6.84 A

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 26

Determine V0 ( in Volts) in the given network.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 26 Applying current-divider,

Hence,

V0 = 4 × I2 = 4 × 6.25× = 25V

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 27

In the figure shown below, ‘N’ is two port network. If I = 2 A, then the values of V1 and V2 will be

Assume the Y - parameter matrix for ' N′ as

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 27 Y- parameter of Network 'N'

I1 = 2V1 + V2........(i)

I2 = 2V1 + 2V2 ........ (ii)

Applying KCL at input node,

Applying KCL at output node,

Putting the value of I1 and l2 in equation (iii) and (iv),

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 28

Find the value of y{z), n > 0 if y(n) + (n - 1 ) - (n ~ 2) = 0 and y(-1) = y { - 2) = 1?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 28 Given y{n) + y{n - 1) - y(n - 2) = 0

Y (-1)= y (-2 ) = 1

Apply Z-transform to the above equation, we get

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 29

Let the state transition matrix of a system be given as

Then which of the following is equal to

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 29 We have,

Hence, replace ′t′ in state transition matrix by '-t'.

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 30

The full-load torque angle of a synchronous motor at rated voltage and frequency is 30° elect. The stator resistance is negligible. ______ degree will be the torque angle if the load torque and terminal voltage remaining constant, the excitation and frequency are raised by 10%


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 30 The answer is in between 33 and 34

Assuming Ra to be negligible,

sin δ = 1.1 sin 30 = 0.55

8 = 33.36

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 31

If 2,3 and 5 are the three Eigen values of a matrix A3 x 3 Then, I Adj A I=


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 31 |A| = 2 × 3 × 5 = 30

|Adj A| = |A|n−1 = |A|2 = (30)2 = 900

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 32

Below figure shows the frequency Response of a lead compensator in which the lead compensator coefficient is _______


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 32

The answer is in between 0.49 and 0.51f

on comparing, 20 log α = −6

log α = −0.3

α = 0.501

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 33

In a system of 132 kV, the line to ground capacitance is 0.01 μF and the inductance is 5 henries. The voltage appearing across the pole of a C .B, if a magnetising current of 5A (instantaneous value) is interrupted and also the value of resistance to be connected across contacts of C .B . to eliminate the restriking voltage is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 33

V = 111.8 KV

In order to eliminate the transient critically the value of resistance across the breaker contacts required

i.e

= 0. 5 × 109 x√5

R = 11.18 KO

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 34

A 10 μF condenser is connected in series with a coil having inductance of 25 mH. If a 100 V source operating at resonance frequency causes a circuit current of 10 mA . What is the Q-factor of the coil?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 34

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 35

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 35

Given

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 36

The transfer characteristics of a Schmitt trigger is shown below:

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 36

Hysteresis voltage;

VH = [VUTP – VLTP]

VH = [2 – (–3)] = 5 V

A clockwise circulating noise eliminating loop corresponds to an inverted Schmitt trigger.

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 37

An A .C Bridge as shown in the figure is used to measure unknown inductance L1, in companion with capacitance. What would be the quality factor if the frequency is 1500 Hz & the various parameter are as below –

R2 = 360 Ω, R3 = 720 Ω, R4 = 1200 Ω & C4 = 1.2 Μf


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 37

The answer is in between 13 and 14

At Balance condition:

On separating real & imaginary part we get,

&L1 = R2R3C4 = 360 × 720 × (1.2 × 10−6) = 0.311H

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 38

Two identical unloaded generators are connected in parallel as shown below. Both the generators are having positive, negative and zero sequence impedance of j0.8 p.u., j 0.2 p.u. and j 0.3 p.u. respectively. If pre-fault voltage is 1 p.u. for a line to ground fault at the terminals of the generator, the fault current magnitude (in p.u.) is ___________. (Assume neutral impedance, Zn = j0.02 p.u.)

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 38

The positive sequence reactance,

Similarly, the equivalent negative sequence reactance is

The zero-sequence reactance diagram is

For a single line to ground fault, fault current is

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 39

In the given figure, a V volt Battery is connected across the capacitor, galvanometer shows the deflection of found. The switch is closed at t = 0. If distance between the plate of capacitor is increased after which the switch is removed from the circuit. What will be effect on Vc capacitor voltage & electric field .

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 39

When the switch is closed for a long line then capacitor will charges up to Vc = V volt.

Now as the switch is removed as shown in figure.

The charge Q across the plate of capacitor are trapped.

After removing the switch distance between the plate of capacitor to increased.

therefore C w ill decrease.

as the charge are trapped i.e; constant.

So where VC is decreased therefore Vc will increases.

So, E remain constant.

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 40

One transformer is rated at 400 KVA & has per unit impedance of (0.02 + j0.08) p.u. and other is rated at 800 KVA & has per unit impedance of (0.20 + j0.08) p.u. Both transformers are connected in parallel to the load. Find the maximum load (in KVA) that can be imposed to transformer’s such that no transformer is overloaded.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 40

The answer is in between 1197 and 1200

Let choose 800 KVA as base KVA.

NOTE: Transformer having the least p.u. impedance saturates first.

So, the max. load is shared when transformer T2 Share its rated load.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 41

Consider both the op-amps are ideal, find out the value of (V01 – V02) in volts___________V.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 41

As op-amps are ideal. Its terminal will not draw no current. Thus,

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 42

At a particular instant, the R-phase voltage of a balanced 3-Φ system is +60 V, and Y-phase voltage is –120 V. The voltage of B-phase at that instant is ____ (in V).


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 42

The answer is in between 58 and 62

For balanced 3 — ф system, V R (t) = V m sinwt

VY ( t ) = V m sin (wt — 120°)

VB(t) = Vmsin (wt + 120°)

Given: V m sinwt = 60 . . . (i) V m sin (wt — 120°) = —120

Vm [sinwtcos 120° — cos wt sin 120°] = —120

cut = 30° Equation

(i) 2+ Equation

(ii) 2 Vm2 sin 2wt + V m 2 cos 2wt = (60)2 + (60√3)2

Vm2[sin 2wt + cos 2wt] = (60)2 + (60-√/3)2

Vm = 120V

VB = V m sin (wt + 120°)

VB = 120 sin (30° + 120°)

VB = 120 sin 150° = 120 x ½ = 60 volts

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 43

The value o f function x(t) at t =


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 43

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 44

For a 6-bit ADC, having full scale deflection of 10volts, the quantization error in millivolts would be________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 44

The answer is in between 79 and 80

Quantization error

= 0.07936volt

= 79.36 mV

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 45

The area bounded by the curve y = x2 and y = 1 – x2 is


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 45

The answer is in between 0.9 and 1

Given that R: y = x2 &t/ = 1 — x2

The point of intersection of the curves y = x 2 & y = 1 — x 2 are given by

X2 = 1 - X2

are the point of intersection of a curves.

The required are is given by

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 46

If the Size of data bus is 16 bits and the size of address bus is 20 bits. Then the processor will be of:

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 46

The size of processor depends only on size of data bus. Here the size of data bus is 16bits. Hence the size of processor will also be 16bits.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 47

For nMOS and its Transfer curve shown in fig. below, Its region of operation is:

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 47

From Transfer curve.

VT = 1 V

From the circuit,

VGS = VG – VS = 3 – 1 = 2 V

VDS = VD – VS = 5 – 1 = 4 V

VGS = VT = 1 V

Since, VDS > VGS – VT

The MOSFET operates in saturation region.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 48

Consider the system described by following state space equations

For the state x3, which one of the options is correct.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 48

Since A is a diagonal matrix, Also all the eigen values are distinct.

x3 is controllable because the 3rd element in the row of B is non zero.

x3 is unobservable because the 3rd element in the column of C is zero.

Thus, option D is the correct answer.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 49

Evaluate where C is circle \z\ = 3

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 49

Poles z = 1&2 both are inside the |z| = 3

f(z) = cos πz2 is an analytic function

= 2πif(1) + 2πif(2)

= 2πi[− cos π + cos 4π]

= 4πi

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 50

Consider the following synchronous counter made up of JK, D and T Flip-Flops.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 50 Consider characteristic equation of here

Consider characteristic equation of D− Flip-Flop.

(ii) Consider characteristic equation of T - Flip-Flop Consider charactrisic

Using equations (i), (ii) and (iii)

The number of used states = 5

∴ Modulus value = 5

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 51

Let the transfer function of a stable discrete time system be H(z). The pole zero diagram of H (z) is shown in the figure below.

Assume that system is causal and stable, then which of the following statements can be true.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 51

Since the system is stable and causal thus all the poles must lie inside the unit circle and for the system to be all-pass system the condition is

⇒ the distance of poles from origin

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 52

Considering a clamper circuit, where capacitance C, load R, the cut-in voltage of diode are unknown.

Which is the correct statement?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 52

The shape and peak to peak value of signal remain unchanged in a clamper.

A clamper only affects the DC voltage level of the wave, which can be both moved up and down, not simply up.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 53

Find the differential gain

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 53

IE1 + IE2 = 2mA

In the differential amplifier, the transistors are biased at same operating points.

Ic1 + Ic2 = 1mA

rc = 25Ω

The formula for the differential gain Ad = -gmRc =

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 54

In a 3 phase, 3 wire system the conductors are arranged in a horizontal plane with spacing D13 = 4m, D12=2m=D23. Conductors are transposed having diameter of 2.5cm. The ratio of mutual GMD to self GMD =?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 54

Mutual GMD =

Self GMD = 0.7788 ×

The ratio of mutual GMD to self GMD = 2.52/9.73x10−3 = 258.84

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 55

A 1200V, 6pole, 50Hz, 3-phase star connected induction motor has stator to rotor turns ratio of 3. At standstill, its rotor impedance is (0.4+j8)Ω/phase. What is the gross output of motor at the speed of 960 rpm in kW? [Write the answer upto three decimal Points]


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 55 Stator phase voltage =

Standstill ratar emf, E 2 =

Synchronous speed of mator Ns =

Slip

Er = sE 2 = 0.04 x 230.94 = 9.4238V

Rator impedance at 0.04 slip Zr =

18.04ATotalCu loss

= 31 2R = 3 x 18.042 x 0.4 = 3 9 0 .6 W

arassautputpowerafmatar 1 — s

Grassoutput =

gross output =

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 56

A two generator system supplying a load of 40MW connected at bus 2. The fuel costs of generators are:

C1(PG1) = 8500 Rs/MWh

C2(PG2) = 11000 Rs/MWh

The loss in the line is Ploss(p.u.)=0.5PG1(p.u.)2 where the loss coefficient is specified in p.u. on a 100 MVA base. The most economic power generation schedule (in MW) is:

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 56

From coordination equation,

(dFn/dPGn){1/ (1-∂PL/∂PGn)} =λ

Given,

PL=0.5PG12

∂PL/∂PG1=PG1 and ∂PL/∂PG2=0

(dF1/dPG1)(1/ (1-PG1) = (dF2/dPG2) (1/ (1-0)

Or, 8500(1/ (1-PG1) = 11000

Or, PG1=0.227 p.u.

As the base value is 100MVA.

PG1=100x0.227 = 22.7MVA

PL= 0.5x(0.227)2 = 0.0258 p.u. = 0.0258x100 MVA = 2.58MVA

PD=PG1+ PG2- PL

Or, 40=22.7+ PG2-2.58

Or, PG2=19.9 MVA

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 57

A unity feedback control system is characterized by the open loop transfer function

The Nyquist path and the corresponding Nyquist plot of G(s) are shown in figures below. If 0< /><1 the="" number="" of="" poles="" of="" the="" closed="" loop="" transfer="" function="" that="" lie="" in="" the="" right="" half="" of="" the="">

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 57

Where, N = number of encirclements of the critical point.

P = number of open loop poles lying in the RHS of s-plane.

Z = number of closed loop poles lying in the RHS of s-plane.

Here 0

Now finding value of P

Use Routh array to find the number of roots of open loop system lying in the RHS of s-plane.

S3+as2+b

Since a>0, b>0

Therefore, number of sign changes = 2

Hence, P = 2

So, N = P-Z

0 = 2-Z

Z = 2

Hence, two closed loop poles are lying in the RHS of s-plane.

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 58

Find the Thevenin equivalent voltage across x-y terminals.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 58

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 59

Energy of signal whose fourier transform is shown in figure equals to


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 59

According to Parseval's Energy theorem

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 60

A boost converter is shown in the figure.

If Vs = 20V, V0 = 60V, R = 60Ω, L = 30 μH and D (duty cycle) = 0.Then the converter will operate at a switching frequency (in kHz) approx. _________.


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 60 For boost converter

V0 >V0

So, the converter is operating in discontinuous mode.

Inductor current waveform will be

When CH is ON

When CH is OFF

From (i) and (ii)

From power balance

For boost converter

Is = IL = 3A

Average inductor current from the waveform

Ip = 8A

From (i)

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 61

For the power system shown below

the zero sequence reactance in pu are indicated. What is the zero sequence driving point reactance of the bus 3 in pu?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 61

So, zero sequence driving point reactance at bus 3;

Xo = (0.22 × 0.3)/(0.22 + 0.3)

Xo = 0.1269 ≈ 0.13pu

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 62

If z(x,y) = x2 – y2 , x(t) = t – t-2 and y(t) = t2 + t-3

Then dx/dt at t=1 is equla to …………..


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 62

Using chain rule

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 63

The given rectifier circuit has a source voltage of 150 sin ωt, and a load resistor of 40 Ω. Determine the average load current, if the thyristors are fired at ωt = 30°

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 63

Given, Vm = 150 V,Rl = 40Ω,α = 300

The output voltage is computed as,

Substituting values,

The average load current is given as,

Gate Mock Test: Electrical Engineering(EE)- 2 - Question 64
Magnesium vapour in a filament lamp gives
Gate Mock Test: Electrical Engineering(EE)- 2 - Question 65

A power system is comprised of three elements 0 – 1, 1 – 2, and 2 – 0 of equal pu impedances of 0.25. Determine the bus impedance matrix of the network

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 2 - Question 65

where y10 = y12 = y20 =

The bus admittance matrix can be written as

The bus impedance matrix pan be computed as

(y bus) det (Ybus) = (8 x 8) - ( - 4 x - 4) = 48

adjoint (ybus) =

Hence Z bus =

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