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Gate Mock Test: Electrical Engineering(EE)- 6


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65 Questions MCQ Test GATE Electrical Engineering (EE) 2023 Mock Test Series | Gate Mock Test: Electrical Engineering(EE)- 6

Gate Mock Test: Electrical Engineering(EE)- 6 for GATE 2022 is part of GATE Electrical Engineering (EE) 2023 Mock Test Series preparation. The Gate Mock Test: Electrical Engineering(EE)- 6 questions and answers have been prepared according to the GATE exam syllabus.The Gate Mock Test: Electrical Engineering(EE)- 6 MCQs are made for GATE 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Gate Mock Test: Electrical Engineering(EE)- 6 below.
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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 1

Question 1 to 5 carry One Mark each

Q.

Even as the ________else where in the world are struggling, to come out of recession, Indian consumers are splurging on consumer goods and to ____________this growth, companies are investing heavily in various sectors.

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 2

In the olympic games, the flags of six nations were flown on the masts in the following way. T he flag of
America was to the left of Indian tricolor and to the right of the flag of france. T he flag of Australia was on
the right of the Indian flag but was to the left of the flag of Japan, which was to the left of the flag of China.
T he two flags which are in the centre is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 2

India and Australia
[France – America – India –Aus. –Japan – China]

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 3

From the given equilateral triangle below A, B and C run along the sides in clockwise direction and stop after coming   sides. Which of the following statements is true?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 3

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 4

In the following questions, a sent ence has been given in direct/indirect speech.
Nitin said to me, “why don’t you come with us? why do you want to be so unsocial.

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 5

Select the grammatical e rror part

In order to transfer (a)/ branch licenses for one (b)/ bank to anot her you require special approval from RBI
(c)/ No error (d).

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 6

Question 6 to 10 carry Two Marks each

Q.

In an NGO, t he daily average wages of 20 illiterate employee is decreased from Rs. 25 to Rs. 10. T hus the
average salary of all the literate (educated) and illiterate employees is decreased by Rs. 10 perday. T he
number of educated employees working in the NGO is

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 7

Directi on for questi ons (7-8).
Answer the question with the help of the following table

Q.

The ratio of the percentage share of Dairy Milk to that of other is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 7

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 8

Answer the question with the help of the following table

Q.

If in the next year, Crackle and Dairy Mill decided to join hands and increase their market share from their
combined existing share by 20%. What will be their combined production if the mark size remains the same?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 8

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 9

Simple interest on a certain amount is 9/16  of the principle. If the number represent ing the rate of intersest in percent and time in years be equal. Then time, for when the principal is lent out is,

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 9

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 10

If A is a square matrix of order 3 and |A| =1/2. The A (a dj(A)) is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 10

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 11

Question 11 to 35 carry One Mark each

Q.

If the probability for A to fail in an examination is 0.2 and that for B is 0.3, then the probability that either A or B fails is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 11

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 12

Eigen value of unit ary matrix are always

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 12

The eigen value of unitary matrix are always of unit modulus

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 13

The linear approximat ion of e–x in the neighbourhood of x = 2 is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 13

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 14

If   , then the value of  is


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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 15

State equation of a cont rol system is given by

T he state transition matrix is .

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 15

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 16

he value of 'k' and 'a' to satisfy the frequency domain specification Mr = 1.04 and ωr = 11.55 rad/sec is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 16

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 17

The current waveform across a 8H inductor is

The voltage wareform is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 17

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 18

For the circuit shown in figure diode cut in voltage is Vin = 0. T he Ripple voltage to not more than Vrip= 4V.
The min load resistance(in k), that can be corrected to the output is

____________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 18

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 19

A bidirectional 4-bit shift register is storing the nibble 1101. Its  input is high. The nibble 1011 is waiting to be entered on the serial data-input line. After these clock pulses, t he shift register is storing (in binary system) _________________


Gate Mock Test: Electrical Engineering(EE)- 6 - Question 20

Use of the reverse conducting thyristor in place of antiparallel combinat ion of thyristor and feedback
diode in an invert er

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 21

Consider a long two wire line composed of solid round-conductors. The radius of bot h conductors is 0.20 cm and the distance between their centres is 2m. If this distance is doubled, t hen the inductance per unit length

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 21

Inductance per wait length = 

μ = Permeability of material
D = Distance between their
cont res
r = Effective radius
L α lo D
If D is double, 1 will increase but does not double.

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 6 - Question 22

If the discharge voltage of a thyrit e arrester is 373 kV rms and the rated voltage is 211 kV rms. T he
discharge factor of the arrester is _______________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 22

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 23

The full load slip of a 3-phase squirrel cage induction motor is 0.05. The start ing current is 5 times the rated current . The ratio of start ing torque to full load torque is ____________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 23

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 24

The volt age |Vab| in the circuit given below is

__________________

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 24

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 6 - Question 25

The common base amplifier is drawn as a two port in figure. The parameter are β= 100, gm = 3mS, r0= 800 k The h parameter h21 is

______________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 25

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 26

A 6 pole, 3-φ, 440V, 50 Hz induction motor has the rotor impedance of (0.2 + j1.6), the ratio of stator to
rotor turns is 1.79 and the full load slip is 0.06. T he full load torque is (in N-m) ______________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 26

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 27

A waveform shown in the figure below is read by AC ammeter. T he reading shown by the meter is
(in mA)

________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 27

Reading of ac ammeter = rms valve

Where, α = duty cycle

Rms valve = 100 mA 

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 28

The NMOS transistor has  If ID = 0.4 mA &
VD = 0.5V. T he values of RD and RS are respectively

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 28

VD = 0.5 is greater than VG, this means nMOS operating in saturation

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 29

A three phase half controlled bridge convert er in continuous conduction mode operat es at a firing angle of 45°, the power factor on the line side is

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 30

The Phase and gain margin margins of the system shown in figure wh ere k = 10 is

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 31

A feedback control system has an open loop transfer function of

The maximum range of k for the closed loop stability is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 31

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 32

  full converter is delivering a constant load current of 60 A at 230 V DC. T he average current of SCR's and r.m.s. current sourc e respectively

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 32

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 33

A DC distribution system is shown in figure with load currents as marked. T he two ends of the feeder are
fed by voltage sources such that VP, VQ = 4V T he value of the voltage VQ for a minimum voltage of 220V
at any point along the feeder is

___________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 33

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 34

A 400V/100V, 10 kVA two winding transformer is reconnected as an autot ransformer across a suitable
voltage. The maximum rating of such a transformer could be (in k)


Gate Mock Test: Electrical Engineering(EE)- 6 - Question 35

Two transformer with leakage impedance  Z1 = 0.1 + j0.4 and Z2 = 0.05 + j0.2 are connected in parallel. T he ratio of load shared   will

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 35

T he sharing of load is inversely proportional to the impedance of the transformer.

 

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 6 - Question 36

Question 36 to 65 carry Two Marks each

Q.

The modulus part of (1 + i)8 is _____________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 36

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 37

The node voltage V1 and V2 of the given circuit is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 37

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 38

In a 3-phase, double layer winding with 9 slot s per pole. Phase spread is kept constant at 60° (electrical).
If the number of slots per pole is double t he new distortion factor will be times the old distribution factor


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 38

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 39

If the phase angle at gain crossover frequency is estimat ed to be –105°. T he value of phase margin of
the system is

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 6 - Question 40

Consider the n-MOS common gate circuit. The parameter  gm = 2mS & ro= ∞ T he voltage gain AV is

____________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 40

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 41

A chopper circuit shown below has input DC voltage of 200V and a load of   In series with L = 80 mH. If load current varies linearly between 12A and 16A, then time ratio  for this chopper is

____________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 41

 

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 42

The 8–input XOR circuit shown has an output of y = 1. Which input combination below (ordered A-H) is
correct?

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 43

f(x, y, z) = xy2 + yz3, the directional derivative of f(x ,y, z) at t he point (2, –1, 1) in the direction of vector

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 43

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 44

If a vector   is defined as  The divergenc e of vector is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 44

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 45

The thevenin equivalent of the given circuit cross AB is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 45

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 46

How many times loop will excess?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 46

Loop exec ute if Z = 1 (Set)
0 time loop will be execute

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 47

An impedance Z0 = (1 + j4) is connected in series with the secondary winding of an ideal transformer as
shown in the figure.

The value of series impedance when referred to the primary side is

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 48

The signal X(t) is

T he signal  will be

*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 6 - Question 49

Using Sim pson’s 1/3rd rule with step size of 0.1, the value of  is___________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 49

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 50

A 3-phase synchronous generator delivers 10 MVA at a voltage of 10.5 kV. T he line impedance is 5.
T he voltage drop in the line in per unit (in volts)
Use the reference base as 12 MVA at 11 kV.

_________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 50

 

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 51

A function   number of prime implicants and minimized expression is

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 52

Consider the circuit shown given below. The transfer characteristics of circuit is repersented as a

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 52

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 53

A unit y feedback cont rol system whose open-loop transfer function is  The rise time and settling time for tolerance 2% respect ively

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 53

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 54

The peak value of the output of the filter if the input pulse to the filter is shown below

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 54

 

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 55

The solution of the differential equation   

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 55

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 56

The transfer characteristics of an FET is given by the parabola IDS = 10 (VGS + 1)2. If the input is
5cosωot. then variation of gm with time is given by

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 56

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 57

A three phase load of 3000 kVA, 0.8 p.f. is supplied at 11kV from a step-down transformer having a ratio 3:1. The primary side of transformer is connected to a transmision line, the constant s of which are resistance per conductor, 2 ohms, reactance per conducter, 3 ohms. T he resistance and reactance per phase of the primary windings of the transformer (which are star connected) are 5 and 10 respectively, and the corresponding value for the secondary winding (which are delta connected) are 1.5 ohms and 3 ohms respectively. The voltage and power factor at the sending end of the transmission line is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 57

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 58

In a reverse biased abrupt p-n junct ion doping concentrat ion NA = 9 ×1016/cm3 and ND = 1 × 1016/cm3
respectively. In p-n junction total deplet ion layer width 3 μm. T he depletion width on p–side is


*Answer can only contain numeric values
Gate Mock Test: Electrical Engineering(EE)- 6 - Question 59

In the circuit shown below OP-AMP is ideal. The total current (in mA) supplied by 20V voltage supply is
(Assume β of transistor very large)

________________


Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 59

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 60

The deflection of an elect ron beam on a CRT screen is 10mm. Suppose the pre-accelerating anode
voltage is halved and the potential between deflect ing plates is doubled, the deflection of the electron
beam will be (in mm) __________


Gate Mock Test: Electrical Engineering(EE)- 6 - Question 61

Consider the given circuit & waveform for the input diode (cut in voltage Vx= 0)

The waveform of output Vo is

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Gate Mock Test: Electrical Engineering(EE)- 6 - Question 62

Consider the following circuits. From the below circuits. Which one will operate as AC voltage regulator?

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 63

The transfer function of the system whose asymptotic approximation is given in figure below, is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 63

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 64

The Fourier transform of the signal

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 64

Gate Mock Test: Electrical Engineering(EE)- 6 - Question 65

The magnitude current i (in A) at t = 5sec in the circuit given is

___________________

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 6 - Question 65

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