GATE  >  GATE Electrical Engineering (EE) 2023 Mock Test Series  >  Gate Mock Test: Electrical Engineering(EE)- 8 Download as PDF

Gate Mock Test: Electrical Engineering(EE)- 8


Test Description

65 Questions MCQ Test GATE Electrical Engineering (EE) 2023 Mock Test Series | Gate Mock Test: Electrical Engineering(EE)- 8

Gate Mock Test: Electrical Engineering(EE)- 8 for GATE 2022 is part of GATE Electrical Engineering (EE) 2023 Mock Test Series preparation. The Gate Mock Test: Electrical Engineering(EE)- 8 questions and answers have been prepared according to the GATE exam syllabus.The Gate Mock Test: Electrical Engineering(EE)- 8 MCQs are made for GATE 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Gate Mock Test: Electrical Engineering(EE)- 8 below.
Solutions of Gate Mock Test: Electrical Engineering(EE)- 8 questions in English are available as part of our GATE Electrical Engineering (EE) 2023 Mock Test Series for GATE & Gate Mock Test: Electrical Engineering(EE)- 8 solutions in Hindi for GATE Electrical Engineering (EE) 2023 Mock Test Series course. Download more important topics, notes, lectures and mock test series for GATE Exam by signing up for free. Attempt Gate Mock Test: Electrical Engineering(EE)- 8 | 65 questions in 180 minutes | Mock test for GATE preparation | Free important questions MCQ to study GATE Electrical Engineering (EE) 2023 Mock Test Series for GATE Exam | Download free PDF with solutions
1 Crore+ students have signed up on EduRev. Have you?
Gate Mock Test: Electrical Engineering(EE)- 8 - Question 1

Let P(E) denote the probability of the event E. Given P(A) = 1, P(B) = 1/2, the values of P(A/B) and P(B/A) respectively are ____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 1


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 2

A vector is solenoid if    

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 3

Let A, B, C, D be n x n matrices, each with non-zero determinant, If ABCD = I, then B-1 is    

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 3

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 4

When a voltage V0 sin ω0t applied to pure inductor the current through it is l0. If the voltage applied is - V0 sin ω0t + 2 V0 sin 2 ω0t + 3 V0 sin 3 ω0t - 4 V0 sin 4 ω0t, thecurrent through inductor is ___   

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 4

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 5

A 1st order system is subjected to step input. Its time constant can be defined as

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 6

With introduction of derivative error compensation

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 7

A system has natural frequency and damping frequency as 10 and 8 rad/sec respectively. Its resonant frequency is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 7



Gate Mock Test: Electrical Engineering(EE)- 8 - Question 8

The eddy current damping can’t be applied to    

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 9

Which one of the following is equivalent to AND-OR realisation?

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 10

The number of pins of 4 k x 16 ROM is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 10

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 11

The address location of 'RST 5’ is _____

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 12

For the circuit shown in below figure, the quiescent point is ___

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 12

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 13

Thermal runaway is not possible in FET because as the temperature of FET increases

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 14

Inverse Laplace transform of the function is ___________

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 14


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 15

Consider the following statements regarding a linear discrete-time system 

1. The system is stable.
2. The initial value h(0) of the impulse response is -4.
3. The steady-state output is zero for a sinusoidal discrete time input of frequency equal to one-fourth the sampling frequency.

Which of these statements are correct?

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 15


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 16

If a function f(t) u(t) is shifted to right side by t0, then the function can be expressed as    

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 17

If a combination of HRC fuse and circuit breaker is used, the C.B. operates for

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 18

As length of the line increases chargingreactance_____  

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 19

In BWR (Boiler Water Reactor) the purposeof water is as    

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 20

Which of the following conditions is/are desired in shunt generator______ 

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 21

The usual test for determining the efficiencyof a traction motor is _______

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 22

In general in a squirrel cage induction motoras the load increases

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 23

The operating mode of synchronous generator while delivering reactive power to grid is    

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 24

For a thyristor delay time, rise time and spread time respectively are td, tr and tp . The turn on time of thyristor would be _______

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 25

In a semiconverter, for firing angle equal to 105° and extinction angle equal to 95°, free wheeling diode conducts for ____

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 26

The steady state current through '1 H' inductor in the circuit shown in below figure is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 26


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 27

The equivalent capacitance between terminals A and B is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 27


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 28

The value of integralwhere c is the circle | z | = 1 is

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 28




Gate Mock Test: Electrical Engineering(EE)- 8 - Question 29

The current flowing through circuit shown in below figure is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 29


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 30

Consider the system shown in below figure by choosing suitable choice of k, the oscillating frequency of the system is ___

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 30



Gate Mock Test: Electrical Engineering(EE)- 8 - Question 31

The step response of a closed loop unity feed back control system is given by c[t] = k[1 - 1.66 e-8t sin (6t + 37°)]. The closed loop transfer function of this system is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 31




Gate Mock Test: Electrical Engineering(EE)- 8 - Question 32

The transfer function of a 2nd order system is Its magnitude at resonant frequency for the unit step input is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 32


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 33

It is desired to measure the voltage across a 50 kΩ resistor in the circuit shown in below.If the voltmeter sensitivity is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 33


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 34

For the ring counter shown in the figure below, is the initial state of counter Q3 Q2Q1 Q0 = 0011. This counter is a ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 34




Gate Mock Test: Electrical Engineering(EE)- 8 - Question 35

Time taken by 2 MHz, 8085 microprocessor to execute the following program is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 35

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 36

A current amplifier has an input resistance of 10 Ω, an output resistance of 10 kΩ and current gain of 1000. If it is feed by a current source having to a 10 kΩ load resistance,then its power gain is____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 36





Gate Mock Test: Electrical Engineering(EE)- 8 - Question 37

Match List-I with List-II and select the correct answer using the codes given below the lists:

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 38

The Fourier transform of   then the Fourier transform of is _______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 38



Gate Mock Test: Electrical Engineering(EE)- 8 - Question 39

Consider the power system shown in below figure.

The receiving end reactive power (QR) is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 39

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 40

The fault impedence of the network with p.u. impedences as shown in below figure is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 40



Gate Mock Test: Electrical Engineering(EE)- 8 - Question 41

A 75 km long overhead line with resistance of 0.034 Ω/km and inductance of 0.54 Ω/ km for 400 kV quadrilateral conductors is to be used to transport 1800 MW at 0.9 p.f. If the line is assumed to be short transmission line, then the sending end voltage should be ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 41




Gate Mock Test: Electrical Engineering(EE)- 8 - Question 42

A long shunt dynamo running at 1000 rpm supplies 33 kW at a terminal voltage of 220 V. The resistance of the armature shunt field and series field are 0.05 Ω, 10.0 Ω and 0.06 Ω respectively. The overall efficiency at the above load is 88%. The torqueexerted by the prime mover is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 42


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 43

A 500 V, 40 kW, 1000 rpm d.c. shunt motor has on full load efficiency of 80%. The armature circuit resistance is 0.125 Ω and the field current is 5A. The resistance to be inserted in armature to limit starting current to 1.65 times the full load current, is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 43


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 44

A squirrel cage type induction motor when started by means of a Y/Δ starter takes 150% of full load line current and develops 45% of full load torque at starting. If an auto transformer is employed with 75% tapping, the starting torque developed by the motor is ____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 44



Gate Mock Test: Electrical Engineering(EE)- 8 - Question 45

In the circuit shown below, thyristor is triggered for 25 μs. The latching current of thyristor is 20 mA. For successful turn on of thyristor the maximum possible value of resistance (R1) is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 45

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 46

A voltage source 200 sin 314t supplies load 50 Ω through a controlled thyristor which performs halfwave rectification. If firing angle is 30° with respect to supply voltage waveform, the average power in the load is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 46



Gate Mock Test: Electrical Engineering(EE)- 8 - Question 47

Match List-I (Chopper) with List-ll (Vin/Vout) by considering Ton = 40 ms and Toff = 160 ms and select the correct answer using the codes given beiow the lists.

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 47





Gate Mock Test: Electrical Engineering(EE)- 8 - Question 48

Two 490 kW transformers each has a maximum efficiency of 98%, but in one the max efficiency occurs at full load while in other, it occurs at half load. Each transformer is on full load for 4 hours, on half load for 6 hours and on one tenth load for 14 hours per day

Q.

The total loss of transformer 1 in a day is _____

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 49

Two 490 kW transformers each has a maximum efficiency of 98%, but in one the max efficiency occurs at full load while in other, it occurs at half load. Each transformer is on full load for 4 hours, on half load for 6 hours and on one tenth load for 14 hours per day

Q. 

The all day efficiency of transformer 2 is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 49





Gate Mock Test: Electrical Engineering(EE)- 8 - Question 50

A 2 bus power system is shown in below figure.

Q. 

A static capacitive reactor of 1 p.u. per phase is connected through a switch at motor bus bar. The steady state power limit of the system with capacitive reactance is ____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 50




Gate Mock Test: Electrical Engineering(EE)- 8 - Question 51

A 2 bus power system is shown in below figure.

Q. 

If the capacitive reactor is replaced by an inductive reactor the steady state power limit
will be _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 51

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 52

Given a > 0, we wish to calculate its reciprocal value 1/a by using Newton Raphson Method for f(x) = 0

Q.

The Newton Raphson algorithm for the function will be ____ 

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 52




Gate Mock Test: Electrical Engineering(EE)- 8 - Question 53

Given a > 0, we wish to calculate its reciprocal value 1/a by using Newton Raphson Method for f(x) = 0

Q. 

For a = 7 and starting with x0 = 0.2, the first two iterations will be ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 53

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 54

The power flowing in a, 3 wire balanced load system is measured by two watt meter method. The reading of watt meter 'A' is 7500 W’ and that of wattmeter B is ‘-1500 W’.

Q.

The power factor of the load is    

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 54

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 55

The power flowing in a, 3 wire balanced load system is measured by two watt meter method. The reading of watt meter 'A' is 7500 W’ and that of wattmeter B is ‘-1500 W’.

Q. 

If the voltage across the capacitor is 400 V, at 50 Hz frequency, the capacitor to be introduced in each phase to make the whole power measured to appear on wattmeter A is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 55





Gate Mock Test: Electrical Engineering(EE)- 8 - Question 56

Physicists dream of a unified theory of matterthat could replace the current ______ ofmutually inconsistent theories and clutter the field

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 57

Direction: The following item consists of a word in capital letters, followed by four words or groups of words. Select the word or group of words that is most nearly opposite in meaning to the word in capital letters.

OBLITERATE

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 58

If Radha borrows 1,00,000 from Rani at the interest rate of 4% on simple interest and lends the same amount to Rajani at the same interest rate on compound interest basis. The net gain to Radha after 5 years is ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 58

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 59

If A : B = 2 : 3, B : C = 2 : 3 and C : D = 4 : 9 then A : D is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 59


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 60

Two taps A and B can fill a tank in 10 hours and 15 hours, respectively. If both the taps are opened together the tank will be full in ______

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 60

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 61

Direction : In the following question, a related pair of words is followed by four pairs of words. Select the pair that best expresses a relationship similar to that expressed in the original pair.

TORRENT: DROPLET

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 62

Direction : The following item, passage consists of six sentences. The first sentence (S1) and the sixth sentences (S6) are given in the beginning. The middle four sentences in each have been removed and jumbled up. These are labelled P, Q, R and S. 

S1 : Freedom and power bring responsibility.
S6 : That future is not one of ease or resting but of incessant striving so that we may fulfil the pledges we have so often taken and the one we shall take today.
P : Some of these pains continue even now.
Q : Before the birth of freedom we have endured ail the pains of labour and our hearts are heavy with the memory of this sorrow.
R : Nevertheless, the past is over and it is the future that beckons to us now.
S : That responsibility rests upon this assembly, a sovereign body representing sovereign people of India.

Q.

Which one of the following is the correctsequence?

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 63

Direction:

(i) In this sentence is underlined in three separate parts and each one is labelled (a), (b) and (c). Read the sentence to find out whether there is an error in any underlined parts (a), (b) or (c), indicate your response on the separate Answer Sheet at the appropriate space. You may feel that there is no error in a sentence. In that case letter (d) will signify a 'No error’ response.
(ii) You are to indicate only one response for each item in your Answer Sheet. (If you indicate more than one response, your answer will be considered wrong.) Errors may be in grammar, word usage or idioms. There may be a word missing or there may be a word which should be removed.
(iii) You are not required to correct the error. You are required only to indicate your response on the Answer Sheet.

Q. 

It is time (a) / you start your studies seriously (b)  / for the exams. (c) / No error. (d)

Gate Mock Test: Electrical Engineering(EE)- 8 - Question 64

If the date 1st January, 1601 falls on Thursday, then the 1st January, 2010 falls on

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 64


Gate Mock Test: Electrical Engineering(EE)- 8 - Question 65

The number of rectangles excluding squares in the mesh shown in below figure is _____

Detailed Solution for Gate Mock Test: Electrical Engineering(EE)- 8 - Question 65

Use Code STAYHOME200 and get INR 200 additional OFF
Use Coupon Code
Information about Gate Mock Test: Electrical Engineering(EE)- 8 Page
In this test you can find the Exam questions for Gate Mock Test: Electrical Engineering(EE)- 8 solved & explained in the simplest way possible. Besides giving Questions and answers for Gate Mock Test: Electrical Engineering(EE)- 8, EduRev gives you an ample number of Online tests for practice