Digital Electronics- 1 - GATE EE Free MCQ Test with solutions

Option B is correct. The essential prime implicants are x' z and x z'.

Using the binary ordering (x y z) with x as the most significant bit, the function is 1 for minterms m1, m3, m4, m5, m6.

x' z covers m1 and m3. y' z covers m1 and m5. x z' covers m4 and m6. Another possible prime implicant is x y', which covers m4 and m5.

A prime implicant is essential if it alone covers at least one minterm. m3 is covered only by x' z, and m6 is covered only by x z'; therefore both are essential.

Since m5 is covered by both y' z and x y', neither of those is essential. Thus the essential prime implicants are x' z and x z', which corresponds to Option B.

When 2 inverters are connected then it will become bi-stable.

A demultiplexer sends a single input to multiple outputs, depending on the select lines. For one input, the demultiplexer gives several outputs. That is why it is called a data distributor.

The symbol itself is that of an AND gate; however, due to the presence of the circle (indicating inversion), it is a Negative-Logic AND gate. This means that when using positive logic (where a high voltage represents a logical '1' and a low voltage represents a logical '0'), the gate behaves oppositely to its symbol.

So, if we convert this negative-logic AND gate into an equivalent positive-logic gate, the inversion circle at the output negates the AND operation, effectively turning it into a NOR gate.

Therefore, the correct answer to the question in the image would be:

2. NOR gate

This is because the NOR gate is the positive-logic equivalent of a negative-logic AND gate.

Option C is correct: B9FFH.

4 k = 4096 = 0x1000.

Last address = start address + size - 1.

AA00H + 1000H = BA00H.

BA00H - 1 = B9FFH.

Therefore, the address of the last byte is B9FFH.

F'S complement of 2BFD is FFF F - 2BFD = D402

A15 A 14 A 13 will be 000 So Range will be

Correct option: A - 0001

Interpret 1011 as a 4-bit two's complement number. Since the MSB is 1, its value is -8 + 0×4 + 2 + 1 = -5.

Interpret 0110 as a 4-bit two's complement number. Since the MSB is 0, its value is 0×8 + 4 + 2 + 0 = 6.

The decimal sum is -5 + 6 = 1.

Adding the 4-bit binaries gives a raw 5-bit sum 10001 (there is a carry-out). In two's complement arithmetic the carry-out from the sign bit is discarded.

Overflow in two's complement occurs only when two operands of the same sign produce a result of opposite sign. Here the operands have opposite signs, so no overflow occurs and the valid 4-bit result is the lower 4 bits: 0001.

Hence the sum expressed in 4-bit two's complement is 0001, which matches option A.