Test: Asynchronous & Synchronous DRAM


20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Asynchronous & Synchronous DRAM


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Attempt Test: Asynchronous & Synchronous DRAM | 20 questions in 20 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
QUESTION: 1

The Reason for the disregarding of the SRAM’s is ________

Solution:

Answer: c
Explanation: The reason for the high cost of the SRAM is because of the usage of more number of transistors.

QUESTION: 2

 The disadvantage of DRAM over SRAM is/are _______

Solution:

Answer: c
Explanation: This means that the cells wont hold their state indefinetly.

QUESTION: 3

The reason for the cells to lose their state over time is

Solution:

Answer: b
Explanation: Since capacitors are used the charge descipates over time.

QUESTION: 4

The capacitors lose the charge over time due to

Solution:

Answer: a
Explanation: The capacitor loses charge due to the backward current of the transistro and due to the small resistance.

QUESTION: 5

_________ circuit is used to restore the capacitor value.

Solution:

Answer: a
Explanation: The sense amplifier detects if the value is above or below the threshlod and then restores it.

QUESTION: 6

To reduce the number of external connections reqiured, we make use of ______

Solution:

Answer: b
Explanation: We multiplex the various address lines onto fewer pins.

QUESTION: 7

The processor must take into account the delay in accessing the memory location, such memories are called ______

Solution:
QUESTION: 8

To get the row address of the required data ______ is enabled.

Solution:

Answer: b
Explanation: This makes the contents of the row required refreshed.

QUESTION: 9

 In order to read multiple bytes of a row at the same time, we make use of ______

Solution:

Answer: a
Explanation: The latch makes it easy to ready multiple bytes of data of the same row simulteneously by just giving the consecutive column address.

QUESTION: 10

The block transfer capability of the DRAM is called ________

Solution:
QUESTION: 11

The difference between DRAM’s and SDRAM’s is/are ________

Solution:

Answer: d
Explanation: The SDRAM’s make use of clock signals to synchronise their operation.

QUESTION: 12

 The difference in address and data connection between DRAM’s and SDRAM’s is

Solution:

Answer: c
Explanation: The SDRAM uses buffered storage of address and data.

QUESTION: 13

A _______ is used to restore the contents of the cells.

Solution:

Answer: b
Explanation: The Counter helps to restore the charge on the capacitor

QUESTION: 14

The mode register is used to

Solution:

Answer: b
Explanation: The mode register is used to choose between burst mode or bit mode of operation.

QUESTION: 15

 In a SDRAM each row is refreshed every 64ms. 

Solution:
QUESTION: 16

The time taken to transfer a word of data to or from the memory is called as ______

Solution:

Answer: c
Explanation: The performance of the memory is measured by means of latency.

QUESTION: 17

 In SDRAM’s buffers are used to store data that is read or written. 

Solution:

Answer: a
Explanation: In SDRAm’s all the bytes of data to be read or written are stored in the buffer until the operation is complete.

QUESTION: 18

The SDRAM performs operation on the _______

Solution:

Answer: a
Explanation: The SDRAM’s are edge-triggered.

QUESTION: 19

DDR SDRAM’s perform fster data transfer by

Solution:

Answer: b
Explanation: By transfering data on both the edges the bandwidth is effectively doubled.

QUESTION: 20

To improve the data retrieval rate

Solution:

Answer: a
Explanation: The division of memory into two banks makes it easy to access two different words at each edge of the clock.

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