Test: Cache Miss & Hit
10 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Cache Miss & Hit
The main memory is structured into modules each with its own address register called ______
Answer: a
Explanation: ABR stands for Address Buffer Register.
When consecutive memory locations are accessed only one module is accessed at a time.
Answer: a
Explanation: In modular approach to memory structuring only one module can be accessed at a time.
In memory interleaving, the lower order bits of the address is used to
Answer: b
Explanation: To implement parallelism in data access we use interleaving.
The number successful accesses to memory stated as a fraction is called as _____
Answer: a
Explanation: The hit rate is a important factor in performance measurement.
The number failed attempts to access memory, stated in the form of fraction is called as _________
Answer: b
Explanation: The miss rate is key factor in deciding the type of replacement algorithm.
In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.
Answer: b
Explanation: Miss usually occurs when the memory block requiered is not present in the cache.
In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ______
Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.
If hit rates are well below 0.9, then they’re called as speedy computers.
Answer: b
Explanation: It has to be above 0.9 for speedy computers.
The extra time needed to bring the data into memory in case of a miss is called as _____
The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy.
Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss penalty.
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