Test: Cache Miss & Hit


10 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Cache Miss & Hit


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This mock test of Test: Cache Miss & Hit for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 10 Multiple Choice Questions for Computer Science Engineering (CSE) Test: Cache Miss & Hit (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Cache Miss & Hit quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Test: Cache Miss & Hit exercise for a better result in the exam. You can find other Test: Cache Miss & Hit extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

The main memory is structured into modules each with its own address register called ______

Solution:

Answer: a
Explanation: ABR stands for Address Buffer Register.

QUESTION: 2

When consecutive memory locations are accessed only one module is accessed at a time. 

Solution:

Answer: a
Explanation: In modular approach to memory structuring only one module can be accessed at a time.

QUESTION: 3

 In memory interleaving, the lower order bits of the address is used to

Solution:

Answer: b
Explanation: To implement parallelism in data access we use interleaving.

QUESTION: 4

 The number successful accesses to memory stated as a fraction is called as _____

Solution:

Answer: a
Explanation: The hit rate is a important factor in performance measurement.

QUESTION: 5

The number failed attempts to access memory, stated in the form of fraction is called as _________

Solution:

Answer: b
Explanation: The miss rate is key factor in deciding the type of replacement algorithm.

QUESTION: 6

In associative mapping during LRU, the counter of the new block is set to ‘0’ and all the others are incremented by one,when _____ occurs.

Solution:

Answer: b
Explanation: Miss usually occurs when the memory block requiered is not present in the cache.

QUESTION: 7

In LRU, the refrenced blocks counter is set to’0′ and that of the previous blocks are incremented by one and others remain same, in case of ______

Solution:

Answer: a
Explanation: If the referenced block is present in the memory it is called as hit.

QUESTION: 8

If hit rates are well below 0.9, then they’re called as speedy computers. 

Solution:

Answer: b
Explanation: It has to be above 0.9 for speedy computers.

QUESTION: 9

The extra time needed to bring the data into memory in case of a miss is called as _____

Solution:
QUESTION: 10

The miss penalty can be reduced by improving the mechanisms for data transfer between the different levels of hierarchy. 

Solution:

Answer: a
Explanation: The extra time needed to bring the data into memory in case of a miss is called as miss penalty.

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