Test: Caches & Performance of Caches


20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Caches & Performance of Caches


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This mock test of Test: Caches & Performance of Caches for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 20 Multiple Choice Questions for Computer Science Engineering (CSE) Test: Caches & Performance of Caches (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Caches & Performance of Caches quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Test: Caches & Performance of Caches exercise for a better result in the exam. You can find other Test: Caches & Performance of Caches extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

The reason for the implementation of the cache memory is ________

Solution:

Answer: b
Explanation: This difference in the speeds of operation of the system caused it to be inefficient.

QUESTION: 2

The effectiveness of the cache memory is based on the property of ________

Solution:

Answer: a
Explanation: This means that the cache depends on the location in the memory that is referenced often.

QUESTION: 3

The temporal aspect of the locality of reference means

Solution:
QUESTION: 4

The spatial aspect of the locality of reference means

Solution:

Answer: d
Explanation: The spatial aspect of locality of reference tells that the nearby instruction is more likely to be executed in future.

QUESTION: 5

 The correspondence between the main memory blocks and those in the cache is given by _________

Solution:

Answer: b
Explanation: The mapping function is used to map the contents of the memory to the cache.

QUESTION: 6

The algorithm to remove and place new contents into the cache is called _______

Solution:

Answer: a
Explanation: As the cache gets full, older contents of the cache are swapped out with newer contents. This decision is taken by the algorithm.

QUESTION: 7

The write-through procedure is used

Solution:

Answer: c
Explanation: When write operation is issued then the corresponding operation is performed.

QUESTION: 8

The bit used to signify that the cache location is updated is ________

Solution:

Answer: a
Explanation: When the cache location is updated in order to signal to the processor this bit is used.

QUESTION: 9

The copy-back protocol is used

Solution:

Answer: b
Explanation: This is another way of performing the write operation,wherein the cache is updated first and then the memory.

QUESTION: 10

The approach where the memory contents are transfered directly to the processor from the memory is called ______

Solution:
QUESTION: 11

 The key factor/s in commercial success of a computer is/are ________

Solution:

Answer: d
Explanation: The performance and cost of the computer system is key decider in the commercial success of the system.

QUESTION: 12

The main objective of the computer system is

Solution:

Answer: b
Explanation: An optimal system provides best performance at low costs.

QUESTION: 13

 A common measure of performance is

Solution:

Answer: a
Explanation: If this measure is less than one then the system is optimal.

QUESTION: 14

The performance depends on

Solution:

Answer: b
Explanation: The performance of a system is decided by how quick an instruction is brought into the system and executed.

QUESTION: 15

The main purpose of having memory hierarchy is to

Solution:

Answer: d
Explanation: By using the memory Hierarchy, we can increase the performance of the system.

QUESTION: 16

The memory transfers between two variable speed devices is always done at the speed of the faster device. 

Solution:
QUESTION: 17

An effective to introduce parallelism in memory access is by _______

Solution:

Answer: a
Explanation: Interleaving divides the memory into modules.

QUESTION: 18

 The performance of the system is greatly influenced by increasing the level 1 cache.

Solution:

Answer: a
Explanation: This is so because the L1 cache is onboard the processor.

QUESTION: 19

Two processors A and B have clock frequencies of 700 Mhz and 900 Mhz respectively. Suppose A can execute an instruction with an averageof 3 steps and B can execute with an average of 5 steps.For the execution of the same instruction which processor is faster

Solution:
QUESTION: 20

If the instruction Add R1, R2, R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation)

Solution:

Answer: c
Explanation: Pipelining is a process of fetching an instruction during the execution of other instruction.

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