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Computer Science Engineering (CSE) Exam  >  Computer Science Engineering (CSE) Tests  >  Computer Architecture & Organisation (CAO)  >  Test: Hazards of Processor Architecture - Computer Science Engineering (CSE) MCQ

Test: Hazards of Processor Architecture - Computer Science Engineering (CSE) MCQ


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10 Questions MCQ Test Computer Architecture & Organisation (CAO) - Test: Hazards of Processor Architecture

Test: Hazards of Processor Architecture for Computer Science Engineering (CSE) 2024 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Hazards of Processor Architecture questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Hazards of Processor Architecture MCQs are made for Computer Science Engineering (CSE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Hazards of Processor Architecture below.
Solutions of Test: Hazards of Processor Architecture questions in English are available as part of our Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) & Test: Hazards of Processor Architecture solutions in Hindi for Computer Architecture & Organisation (CAO) course. Download more important topics, notes, lectures and mock test series for Computer Science Engineering (CSE) Exam by signing up for free. Attempt Test: Hazards of Processor Architecture | 10 questions in 10 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
Test: Hazards of Processor Architecture - Question 1
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Any condition that causes a processor to stall is called as _____

Detailed Solution for Test: Hazards of Processor Architecture - Question 1

Answer: a
Explanation: An hazard causes a delay in the execution process of the processor.

Test: Hazards of Processor Architecture - Question 2
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The periods of time when the unit is idle is called as _____

Detailed Solution for Test: Hazards of Processor Architecture - Question 2

Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.

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Test: Hazards of Processor Architecture - Question 3
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The contention for the usage of a hardware device is called as ______

Detailed Solution for Test: Hazards of Processor Architecture - Question 3

Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a deadlock state.

Test: Hazards of Processor Architecture - Question 4
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The situation where in the data of operands are not available is called ______
Detailed Solution for Test: Hazards of Processor Architecture - Question 4

Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.

Test: Hazards of Processor Architecture - Question 5
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 The stalling of the processor due to the unavailability of the instructions is called as ____
Detailed Solution for Test: Hazards of Processor Architecture - Question 5

Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a cache miss.

Test: Hazards of Processor Architecture - Question 6
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The time lost due to branch instruction is often referred to as _____
Detailed Solution for Test: Hazards of Processor Architecture - Question 6

Answer: c
Explanation: This time also retards the performance speed of the processor.

Test: Hazards of Processor Architecture - Question 7
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The pipeline bubbling is a method used to prevent data hazard and structural hazards. 
Detailed Solution for Test: Hazards of Processor Architecture - Question 7

Answer: a
Explanation: The periods of time when the unit is idle is called as Bubble.

Test: Hazards of Processor Architecture - Question 8
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_____ method is used in centralized systems to perform out of order execution.
Detailed Solution for Test: Hazards of Processor Architecture - Question 8

Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions.

Test: Hazards of Processor Architecture - Question 9
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The algorithm followed in most of the systems to perform out of order execution is ______
Detailed Solution for Test: Hazards of Processor Architecture - Question 9

Answer: a
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution).

Test: Hazards of Processor Architecture - Question 10
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The problem where process concurrency becomes an issue is called as ______
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