Courses
Get the App Signup / Login

Test: Hazards of Processor Architecture


10 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Hazards of Processor Architecture


Description
This mock test of Test: Hazards of Processor Architecture for Electronics and Communication Engineering (ECE) helps you for every Electronics and Communication Engineering (ECE) entrance exam. This contains 10 Multiple Choice Questions for Electronics and Communication Engineering (ECE) Test: Hazards of Processor Architecture (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Hazards of Processor Architecture quiz give you a good mix of easy questions and tough questions. Electronics and Communication Engineering (ECE) students definitely take this Test: Hazards of Processor Architecture exercise for a better result in the exam. You can find other Test: Hazards of Processor Architecture extra questions, long questions & short questions for Electronics and Communication Engineering (ECE) on EduRev as well by searching above.
QUESTION: 1

Any condition that causes a processor to stall is called as _____

Solution:

Answer: a
Explanation: An hazard causes a delay in the execution process of the processor.

QUESTION: 2

The periods of time when the unit is idle is called as _____

Solution:

Answer: d
Explanation: The stalls are a type of hazards that affect a pipe-lined system.

QUESTION: 3

The contention for the usage of a hardware device is called as ______

Solution:

Answer: a
Explanation: The processor contends for the usage of the hardware and might enter into a deadlock state.

QUESTION: 4

The situation where in the data of operands are not available is called ______
Solution:

Answer: a
Explanation: Data hazards are generally caused when the data is not ready on the destination side.

QUESTION: 5

 The stalling of the processor due to the unavailability of the instructions is called as ____
Solution:

Answer: a
Explanation: The control hazard also called as instruction hazard is usually caused by a cache miss.

QUESTION: 6

The time lost due to branch instruction is often referred to as _____
Solution:

Answer: c
Explanation: This time also retards the performance speed of the processor.

QUESTION: 7

The pipeline bubbling is a method used to prevent data hazard and structural hazards. 
Solution:

Answer: a
Explanation: The periods of time when the unit is idle is called as Bubble.

QUESTION: 8

_____ method is used in centralized systems to perform out of order execution.
Solution:

Answer: b
Explanation: In a scoreboard, the data dependencies of every instruction are logged. Instructions are released only when the scoreboard determines that there are no conflicts with previously issued and incomplete instructions.

QUESTION: 9

The algorithm followed in most of the systems to perform out of order execution is ______
Solution:

Answer: a
Explanation: The Tomasulo algorithm is a hardware algorithm developed in 1967 by Robert Tomasulo from IBM. It allows sequential instructions that would normally be stalled due to certain dependencies to execute non-sequentially (out-of-order execution).

QUESTION: 10

The problem where process concurrency becomes an issue is called as ______
Solution:

Recommended Content

Recommended Tests

Related tests
Follow Us
© EduRev