Test: Interrupts


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30 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Interrupts

Test: Interrupts for Computer Science Engineering (CSE) 2022 is part of Computer Architecture & Organisation (CAO) preparation. The Test: Interrupts questions and answers have been prepared according to the Computer Science Engineering (CSE) exam syllabus.The Test: Interrupts MCQs are made for Computer Science Engineering (CSE) 2022 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Interrupts below.
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Test: Interrupts - Question 1

The interrupt-request line is a part of the

Detailed Solution for Test: Interrupts - Question 1

Answer: b
Explanation: The Interrupt-request line is a control line along which the device is allowed to send the interrupt signal.

Test: Interrupts - Question 2

The return address from the interrupt-service routine is stored on the

Detailed Solution for Test: Interrupts - Question 2

Answer: c
Explanation: The Processor after servicing the interrupts as to load the address of the previous process and this address is stored in the stack.

Test: Interrupts - Question 3

The signal sent to the device from the processor to the device after recieving an interrupt is

Detailed Solution for Test: Interrupts - Question 3

Answer: a
Explanation: The Processor upon recieving the interrupt should let the device know that its request is received.

Test: Interrupts - Question 4

 When the process is returned after an interrupt service ______ should be loaded again.
i) Register contents
ii) Condition codes
iii) Stack contents
iv) Return addresses

Test: Interrupts - Question 5

 The time between the recieval of an interrupt and its service is ______

Detailed Solution for Test: Interrupts - Question 5

Answer: b
Explanation: The delay in servicing of an interrupt happens due to the time taken for contect switch to take place.

Test: Interrupts - Question 6

 Interrupts form an important part of _____ systems.

Detailed Solution for Test: Interrupts - Question 6

Answer: c
Explanation: This forms an imporatant part of the Real time system since if a process arrives with greater priority then it raises an interrupt and the other process is stopped and the interrupt will be serviced.

Test: Interrupts - Question 7

A single Interrupt line can be used to service n different devices? 

Test: Interrupts - Question 8

______ type circuits are generally used for interrupt service lines
i) open-collector
ii) open-drain
iii) XOR
iv) XNOR

Test: Interrupts - Question 9

 The resistor which is attached to the service line is called _____

Detailed Solution for Test: Interrupts - Question 9

Answer: b
Explanation: This resistor is used to pull up the voltage of the interrupt service line.

Test: Interrupts - Question 10

An interrupt that can be temporarily ignored is

Detailed Solution for Test: Interrupts - Question 10

Answer: c
Explanation: The maskable interrupts are usually low priority interrupts which can be ignored if an higher priority process is being executed.

Test: Interrupts - Question 11

The 8085 microprocessor respond to the presence of an interrupt

Detailed Solution for Test: Interrupts - Question 11

Answer: c
Explanation: The 8085 microprocessor are designed to complete the execution of the current instruction and then to service the interrupts.

Test: Interrupts - Question 12

CPU as two modes privileged and non-privileged. In order to change the mode from privileged to non-privileged

Detailed Solution for Test: Interrupts - Question 12

Answer: b
Explanation: A software interrupt by some program which needs some cPU service, at that time the two modes can be interchanged.

Test: Interrupts - Question 13

Which interrupt is unmaskable?

Detailed Solution for Test: Interrupts - Question 13

Answer: c
Explanation: The trap is a non-maskable interrupt as it deals with the on going process in the processor. THe trap is initiated by the process being executed due to lack of data required for its completion.Hence trap is unmaskable.

Test: Interrupts - Question 14

 From amongst the following given scenarios determine the right one to justify interrupt mode of data transfer
i) Bulk transfer of several kilo-byte
ii) Moderately large data transfer of more than 1kb
iii) Short events like mouse action
iv) Keyboard inputs

Test: Interrupts - Question 15

How can the processor ignore other interrupts when it is servicing one

Test: Interrupts - Question 16

When dealing with multiple device interrupts, which mechanism is easy to implement?

Detailed Solution for Test: Interrupts - Question 16

Answer: a
Explanation: In this method the processor checks the IRQ bits of all the devices, which ever is enabled first that device is serviced.

Test: Interrupts - Question 17

 The interrupt servicing mechanism in which the requesting device identifies itself to the processor to be serviced is ___________

Test: Interrupts - Question 18

 In vectored interrupts, how does the device identify itself to the processor?

Detailed Solution for Test: Interrupts - Question 18

Answer: c
Explanation: By sending the starting address of the routine the device ids the routine required and thereby identifying itself.

Test: Interrupts - Question 19

The code sent by the device in vectored interrupt is _____ long.

Test: Interrupts - Question 20

The starting address sent by the device in vectored interrupt is called as __________

Test: Interrupts - Question 21

 The processor indicates to the devices that it is ready to recieve interrupts ________

Detailed Solution for Test: Interrupts - Question 21

Answer: c
Explanation: When the processor activates the acknowledge line the devices send their interrupts to the processor.

Test: Interrupts - Question 22

We describe a protocol of input device communication below:
i) Each device has a distinct address.
ii) The BUS controller scans each device in sequence of increasing address value to determine if the entity wishes to communicate
iii) The device ready to communicate leaves its data in the I/O register
iv) The data is picked up and the controller moves to the step a
Identify the form of communication best describes the I/O mode amongst the following:

Detailed Solution for Test: Interrupts - Question 22

Answer: d
Explanation: In polling the processor checks each of the device if they wish to perform data transfer and if they do it performs the particular operation.

Test: Interrupts - Question 23

Which one of the following is true with regard to a CPU having a single interrupt request line and single interrupt grant line?
i) Neither vectored nor multiple interrupting devices is possible.
ii) Vectored interrupts is not possible but multiple interrupting devices is possible.
iii) Vectored interrupts is possible and multiple interrupting devices is not possible.
iv) Both vectored and multiple interrupting devices is possible.

Test: Interrupts - Question 24

Which table handle stores the addresses of the interrupt handling sub-routines?

Test: Interrupts - Question 25

_________ method is used to establish priority by serially connecting all devices that request an interrupt.

Detailed Solution for Test: Interrupts - Question 25

Answer: b
Explanation: In Daisy chain mechanism, all the devices are connected using a single request line and they’re serviced based on the interrupting device’s priority.

Test: Interrupts - Question 26

In daisy chaining device 0 will pass the signal only if it has _______

Detailed Solution for Test: Interrupts - Question 26

Answer: b
Explanation: In daisy chaining since there is only one request line and only one acknowledge line, the acknowledge signal passes from device to device until the one with the interrupt is found.

Test: Interrupts - Question 27

______ interrupt method uses register whose bits are set seperately by interrupt signal for each device.

Test: Interrupts - Question 28

____ register is used for the purpose of controlling the status of each interrupt request in parallel priority interrupt.

Test: Interrupts - Question 29

The anded output of the bits of the interrupt register and the mask register are set as input of:

Detailed Solution for Test: Interrupts - Question 29

Answer: b
Explanation: In a parallel priority system, the priority of the device is obtained by anding the contents of the interrupt register and the mask register.

Test: Interrupts - Question 30

Interrupts initiated by an instruction is called as _______

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