# Test: Multiple BUS Organisation

## 10 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Multiple BUS Organisation

Description
Attempt Test: Multiple BUS Organisation | 10 questions in 10 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
QUESTION: 1

### The general purpose registers are combined into a block called as ______

Solution:

Explanation: To make the access of the registers easier, we classify them into register files.

QUESTION: 2

### In ______ technology, the implementation of the register file is by using an array of memory locations.

Solution:

Explanation: By doing so the access of the registers can be made faster.

QUESTION: 3

### In a three BUS architecture, how many input and output ports are there ?

Solution:

Explanation: That is enabling reading from two locations and writting into one.

QUESTION: 4

For a 3 BUS architecture, is the below code correct for adding three numbers ?
PCout, R = B, MARin , READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End

Solution:

Explanation: We have assumed the names of the three BUSes has A, B and C.

QUESTION: 5

The main advantage of multiple bus organisation over single bus is __________

Solution:
QUESTION: 6

CISC stands for _________

Solution:

Explanation: The CISC machines are well adept at handling multiple BUS organisation.

QUESTION: 7

If the instruction Add R1,R2,R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).

Solution:

Explanation: The value will be much lower in case of multiple BUS organisation.

QUESTION: 8

In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.

Solution:

Explanation: The MUX can be used to either select the BUS or to increment the PC

QUESTION: 9

There exists a seperate block consisting of various units to decode an instruction.

Solution: