Test: Multiple BUS Organisation


10 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Multiple BUS Organisation


Description
This mock test of Test: Multiple BUS Organisation for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 10 Multiple Choice Questions for Computer Science Engineering (CSE) Test: Multiple BUS Organisation (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Multiple BUS Organisation quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Test: Multiple BUS Organisation exercise for a better result in the exam. You can find other Test: Multiple BUS Organisation extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

The general purpose registers are combined into a block called as ______

Solution:

Answer: c
Explanation: To make the access of the registers easier, we classify them into register files.

QUESTION: 2

 In ______ technology, the implementation of the register file is by using an array of memory locations.

Solution:

Answer: a
Explanation: By doing so the access of the registers can be made faster.

QUESTION: 3

In a three BUS architecture, how many input and output ports are there ?

Solution:

Answer: c
Explanation: That is enabling reading from two locations and writting into one.

QUESTION: 4

For a 3 BUS architecture, is the below code correct for adding three numbers ?
PCout, R = B, MARin , READ, Inc PC
WMFC
MDRout, R = B, IRin
R4outa, R5outb, Select A, ADD, R6in, End

Solution:

Answer: a
Explanation: We have assumed the names of the three BUSes has A, B and C.

QUESTION: 5

The main advantage of multiple bus organisation over single bus is __________

Solution:
QUESTION: 6

 CISC stands for _________

Solution:

Answer: c
Explanation: The CISC machines are well adept at handling multiple BUS organisation.

QUESTION: 7

 If the instruction Add R1,R2,R3 is executed in a system which is pipelined, then the value of S is (Where S is term of the Basic performance equation).

Solution:

Answer: c
Explanation: The value will be much lower in case of multiple BUS organisation.

QUESTION: 8

In multiple BUS organisation __________ is used to select any of the BUSes for input into ALU.

Solution:

Answer: a
Explanation: The MUX can be used to either select the BUS or to increment the PC

QUESTION: 9

There exists a seperate block consisting of various units to decode an instruction. 

Solution:

Answer: a
Explanation: This block is used to decode the instruction and place it in the IR.

QUESTION: 10

There exists a seperate block to increment the PC in multiple BUS organisation.

Solution:

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