# Test: Parallel & Serial Port

## 20 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Parallel & Serial Port

Description
Attempt Test: Parallel & Serial Port | 20 questions in 20 minutes | Mock test for Computer Science Engineering (CSE) preparation | Free important questions MCQ to study Computer Architecture & Organisation (CAO) for Computer Science Engineering (CSE) Exam | Download free PDF with solutions
QUESTION: 1

### The _____ circuit enables the generation of the ASCII code when the key is pressed.

Solution:

Explanation: The signal generated upon the pressing of a button is encoded by the encoder circuit into the corresponding ASCII value.

QUESTION: 2

### To overcome multiple signals being generated upon a single press of the button, we make use of ______

Solution:

Explanation: When the button is pressed,the contact surfaces bounce and hence it might lead to generation of multiple signals.In order to overcome this we use Debouncing circuits.

QUESTION: 3

### The best mode of conncetion between devices which need to send or recieve large amounts of data over a short distance is _____

Solution:

Explanation: The parallel port transfers around 8 to 16 bits of data simultaneously over the lines, hence increasing transfer rates.

QUESTION: 4

The output of the encoder circuit is/are ______

Solution:

Explanation: The encoder outputs the ASCII value along with the valid signal which indicates that a key was pressed.

QUESTION: 5

The disadvantage of using parallel mode of communication is ______

Solution:

Explanation: The parallel mode of data transfer is costly as it involves data being sent over parallel lines.

QUESTION: 6

In a 32 bit processor, the A0 bit of the address line is connected to _____ of the parallel port interface.

Solution:
QUESTION: 7

The Status flag circuit is implemented using _____

Solution:

Explanation: The circuit is implemented using the edge triggered D flip flop, that is triggered on the rising edge of the valid signal.

QUESTION: 8

In the output interface of the parallel port, along with the valid signal ______ is also sent.

Solution:

Explanation: The idle signal is used to check if the device is idle and ready to receive data.

QUESTION: 9

DDR stands for __________

Solution:

Explanation: This register is used to control the flow of data from the DATAOUT register.

QUESTION: 10

In a general 8-bit parallel interface, the INTR line is connected to _______

Solution:
QUESTION: 11

The mode of transmission of data, where one bit is sent for each clock cycle is ______

Solution:

Explanation: In isochronous mode of transmission, each bit of the data is sent per each cycle.

QUESTION: 12

The transformation between the Parallel and serial ports is done with the help of ______

Solution:

Explanation: The Shift registers are used to output the data in a desired format based on the need.

QUESTION: 13

The serial port is used to connect basically _____ and processor.

Solution:

Explanation: The serial port is used to connect keyboard and other devices which input or output one bit at a time.

QUESTION: 14

The double buffer is used for

Solution:
QUESTION: 15

______ to increase the flexibility of the serial ports.

Solution:

Explanation: The ports are made more flexible by enabling the input or output of different clock signals for different devices.

QUESTION: 16

UART stands for ________

Solution:

Explanation: The UART is a standard developed for designing serial ports.

QUESTION: 17

The key feature of UART is

Solution:
QUESTION: 18

The data transfer in UART is done in ______

Solution:

Explanation: This basically means that the data transfer is done in asynchronous mode.

QUESTION: 19

The standard used in serial ports to facilitate communication is _____

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