The duration between the read and the mfc signal is ______
Explanation: The time between the issue of read signal and the completion of it is called memory access time.
The minimum time delay between two successive memory read operations is ______
Explanation: The Time taken by the cpu to end one read operation and to start one more is cycle time.
MFC is used to _________
Explanation: The MFC stands for memory Function Complete.
__________ is the bootleneck, when it comes computer performance.
Explanation: The processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance.
The logical addresses generated by the cpu are mapped onto physical memory by ____
Explanation: The MMU stands for memory management unit, which is used to map logical address onto phsical address.
VLSI stands for ___________
The cells in a row are connected to a common line called ______
Explanation: This means that the cell contents together form one word of instruction or data.
The cells in each column are connected to ______
Explanation: The cells in each column are connected to the sense/write circuit using two bit lines and which is inturn connected to the data lines.
The word line is driven by the _____
A 16 X 8 organisation of memory cells, can store upto _____
Explanation: It can store upto 128 bits as each cell can hold one bit of data.
A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised into _____
Explanation: All the others require less than 10 address bits.
Circuits that can hold their state as long as power is applied is _______
The number of external connections required in 16 X 8 memory organisation is _____
Explanation: In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.
The advantage of CMOS SRAM over the transistor one’s is _________
Explanation: This is because the cell consumes power only when it is being accessed.
In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
Explanation: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation).
The chip can be disabled or cut off from external connection using ______
Explanation: The chip gets enabled if the CS is set otherwise the chip gets disabled.
To organise large memory chips we make use of ______
Explanation: The cell blocks are arranged and put in a memory module.
The less space consideration as lead to the development of ________ (for large memories).
Explanation: The SIMM (single inline memory module) or DIMM (dual inline memory module) occupy less space while providing greater memory space.
The SRAM’s are basically used as ______
Explanation: The SRAM’s are used as caches as their opeartion speed is very high.
The higher order bits of the address are used to _____
The address lines multiplexing is done using ______
Explanation: This unit multiplexes the various address lines to lesser pins on the chip.
The controller multiplexes the addresses after getting the _____ signal.
Explanation: The controller gets the request from the device needing the memory read or write operation and then it multiplexes the address.
The RAS and CAS signals are provided by the ______
Explanation: The multiplexed signal of the controller is split into RAS and CAS.
Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read opeartion. Then the refresh overhead of the chip is ______
Explanation: The refresh overhead is calculated by taking into account the total time for refreshing and the interval of each refresh.
When DRAM’s are used to build a complex large memory,then the controller only provides the refresh counter.