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Test: Static & Large Memories


25 Questions MCQ Test Computer Architecture & Organisation (CAO) | Test: Static & Large Memories


Description
This mock test of Test: Static & Large Memories for Computer Science Engineering (CSE) helps you for every Computer Science Engineering (CSE) entrance exam. This contains 25 Multiple Choice Questions for Computer Science Engineering (CSE) Test: Static & Large Memories (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Static & Large Memories quiz give you a good mix of easy questions and tough questions. Computer Science Engineering (CSE) students definitely take this Test: Static & Large Memories exercise for a better result in the exam. You can find other Test: Static & Large Memories extra questions, long questions & short questions for Computer Science Engineering (CSE) on EduRev as well by searching above.
QUESTION: 1

The duration between the read and the mfc signal is ______

Solution:

Answer: a
Explanation: The time between the issue of read signal and the completion of it is called memory access time.

QUESTION: 2

 The minimum time delay between two successive memory read operations is ______

Solution:

Answer: a
Explanation: The Time taken by the cpu to end one read operation and to start one more is cycle time.

QUESTION: 3

MFC is used to _________

Solution:

Answer: c
Explanation: The MFC stands for memory Function Complete.

QUESTION: 4

__________ is the bootleneck, when it comes computer performance.
Solution:

Answer: b
Explanation: The processor can execute instructions faster than they’re fetched, hence cycle time is the bottleneck for performance.

QUESTION: 5

The logical addresses generated by the cpu are mapped onto physical memory by ____
Solution:

Answer: c
Explanation: The MMU stands for memory management unit, which is used to map logical address onto phsical address.

QUESTION: 6

VLSI stands for ___________
Solution:
QUESTION: 7

The cells in a row are connected to a common line called ______
Solution:

Answer: b
Explanation: This means that the cell contents together form one word of instruction or data.

QUESTION: 8

 The cells in each column are connected to ______
Solution:

Answer: d
Explanation: The cells in each column are connected to the sense/write circuit using two bit lines and which is inturn connected to the data lines.

QUESTION: 9

The word line is driven by the _____
Solution:
QUESTION: 10

A 16 X 8 organisation of memory cells, can store upto _____
Solution:

Answer: d
Explanation: It can store upto 128 bits as each cell can hold one bit of data.

QUESTION: 11

A memory organisation that can hold upto 1024 bits and has a minimum of 10 address lines can be organised into _____
Solution:

Answer: d
Explanation: All the others require less than 10 address bits.

QUESTION: 12

Circuits that can hold their state as long as power is applied is _______
Solution:
QUESTION: 13

The number of external connections required in 16 X 8 memory organisation is _____
Solution:

Answer: a
Explanation: In the 14, 8-data lines,4-address lines and 2 are sense/write and CS signals.

QUESTION: 14

 The advantage of CMOS SRAM over the transistor one’s is _________
Solution:

Answer: d
Explanation: This is because the cell consumes power only when it is being accessed.

QUESTION: 15

 In a 4M-bit chip organisation has a total of 19 external connections.then it has _______ address if 8 data lines are there.
Solution:

Answer: c
Explanation: To have 8 data lines and 19 external connections it has to have 9 address lines(i.e 512 x 8 organisation).

QUESTION: 16

 The chip can be disabled or cut off from external connection using ______
Solution:

Answer: a
Explanation: The chip gets enabled if the CS is set otherwise the chip gets disabled.

QUESTION: 17

To organise large memory chips we make use of ______
Solution:

Answer: c
Explanation: The cell blocks are arranged and put in a memory module.

QUESTION: 18

The less space consideration as lead to the development of ________ (for large memories).
Solution:

Answer: d
Explanation: The SIMM (single inline memory module) or DIMM (dual inline memory module) occupy less space while providing greater memory space.

QUESTION: 19

The SRAM’s are basically used as ______
Solution:

Answer: b
Explanation: The SRAM’s are used as caches as their opeartion speed is very high.

QUESTION: 20

The higher order bits of the address are used to _____
Solution:
QUESTION: 21

The address lines multiplexing is done using ______
Solution:

Answer: b
Explanation: This unit multiplexes the various address lines to lesser pins on the chip.

QUESTION: 22

The controller multiplexes the addresses after getting the _____ signal.
Solution:

Answer: d
Explanation: The controller gets the request from the device needing the memory read or write operation and then it multiplexes the address.

QUESTION: 23

The RAS and CAS signals are provided by the ______
Solution:

Answer: c
Explanation: The multiplexed signal of the controller is split into RAS and CAS.

QUESTION: 24

Consider a memory organised into 8K rows, and that it takes 4 cycles to complete a read opeartion. Then the refresh overhead of the chip is ______
Solution:

Answer: b
Explanation: The refresh overhead is calculated by taking into account the total time for refreshing and the interval of each refresh.

QUESTION: 25

 When DRAM’s are used to build a complex large memory,then the controller only provides the refresh counter. 
Solution:

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