Test: Pipelining- 1 - Computer Science Engineering (CSE) MCQ

In pipelining, a number of functional units are employed in sequence to perform a single computation.

An instruction cycle is the basic operational process of a computer. It is the process by which a computer retrieves a program instruction from its memory, determines what actions the instruction dictates and carries out those actions. Also called as fetch, decode-execute cycle.

Clock period of pipeline = Maximum delay of stages
= Max ( 1, 2, 3, 1, 1) = 3

μ-instruction for fetch cycle:

So, PC, IR and address register are used.

It is the definition of microassembler.

In RISC instruction set all arithmetic/logic instructions must be register-based but not in CISC.

MAR is a register that holds the address of location to or from which data are to be transferred.

For pipeline with K segment and n instruction
Time (pipeline ) = ( K + n - i ) t_P
= ( 4 + 100 - 1 ) x 20 nsec
= (4 + 99) x 20 nsec 
= (103) x 20 nsec = 2060 nsec 

The needed for non pipelined processor

Speedup = 8000/2060 = 3.88

Since the unpipelined machine executes all instructions in a single clock cycle, its average time per instruction is simply clock time. The dock is equal to the sum of the times for each step in the execution.
∴ Average instructions execution time
= 5 + 8 + 6 + 1 0 + 15 + 12 + 6 + 8 
= 70
The dock cycle time on the pipelined machine must be the largest time for any stage in the pipeline (15 ns) + the overhead of 1 ns for a total of 16 ns.
∴ Speed from pipelining