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Test: JK Flip Flop - Electrical Engineering (EE) MCQ


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15 Questions MCQ Test Analog and Digital Electronics - Test: JK Flip Flop

Test: JK Flip Flop for Electrical Engineering (EE) 2024 is part of Analog and Digital Electronics preparation. The Test: JK Flip Flop questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: JK Flip Flop MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: JK Flip Flop below.
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Test: JK Flip Flop - Question 1

Consider the circuit shown below:

The characteristic equation of the new flip-flop created from the above circuit is

Detailed Solution for Test: JK Flip Flop - Question 1

For J-K flip-flop,

Qn+1 = JQ̅n + K̅Qn ----(1)

For the given circuit:

J = X ⊕ Y and K = X

From equation (1);

Qn+1 = (X ⊕ Y)Q̅n + X̅Qn         

= X̅YQ̅n + X̅Qn + XY̅Q̅n 

= X̅Qn + X̅YQ̅n + XY̅Q̅n

= X̅ (YQ̅n + Qn) + XY̅Q̅n

= X̅ (Y + Qn) + XY̅Q̅n

Hence, option 2 is correct.

Test: JK Flip Flop - Question 2

For which of the following flip-flops, the output is clearly defined for all combinations of two inputs.

Detailed Solution for Test: JK Flip Flop - Question 2

For R-S flip-flop for input 1,1 the output is undefined.

The truth table of J-K -flop-flop is

The output is clearly defined for all combinations of inputs.

Both D type and T type flip-flops have only one input.

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Test: JK Flip Flop - Question 3

The functional difference between SR flip-flop and JK flip-flop is that

Detailed Solution for Test: JK Flip Flop - Question 3

In J-K flip flop when both inputs are HIGH, the output toggles i.e. it changes from high to low and low to high periodically when both the inputs are 1.
For an SR flip flop, however, when both the inputs are HIGH, we encounter an invalid state, which is not present for a JK flip flop.
This is explained with the help of the following function table:

​Similarly, for a JK flip flop, the block diagram along with the function table is as shown:

Test: JK Flip Flop - Question 4

The current state QA QB of a two JK flip-flop system is 00. Assume that the clock rise-time is much smaller than the delay of the JK flip-flop. The next state of the system is.

Detailed Solution for Test: JK Flip Flop - Question 4

In the given circuit

We have,

JA = KA = 1


So next state will be 11 

Test: JK Flip Flop - Question 5

The race around condition exists in J – K flip – flop if – 

Detailed Solution for Test: JK Flip Flop - Question 5

When the two inputs of a flip flop are at logical 1 and then the input is changed to any other condition, then the output becomes unpredictable and this is called the race around condition.

The race around condition exists in JK flip flop if J = 1, K = 1.

The race around condition is an undesirable condition as the output of the flip flop cannot be predicted at that moment.

The race around condition can be avoided by using Master Slave flip flop 

Test: JK Flip Flop - Question 6

A synchronous counter using two J – K flip flops that goes through the sequence of states: Q1 Q2 = 00 → 10 → 01 → 11 → 00 …. is required. To achieve this, the inputs to the flip flops are

Detailed Solution for Test: JK Flip Flop - Question 6

By using excitation table of JK flip flop.

From the above table,

Test: JK Flip Flop - Question 7

The output Qn of a JK flip-flop is zero. It changes to 1 when a clock pulse is applied. The input Jn and Kare respectively

Detailed Solution for Test: JK Flip Flop - Question 7

Characteristic Table of JK flip flop is:

Qn+1 = JQ̅n + K̅Qn

Based on the table we can see the correct input combination is 1 0 and 1 1.

∴ Option A is correct. 

Test: JK Flip Flop - Question 8

In a JK flip-flop we have J = Q̅ and K = 1 Assuming the flip-flop was initially cleared and then clocked for 6 pulses, the sequence at the Q output will be:

Detailed Solution for Test: JK Flip Flop - Question 8

Concept:

JK FF truth table

Qn = present state

Qn+1 = next state

Analysis:

Given: initial state cleared so Qn = 0

J = Q̅

K = 1

So the o/p sequence will be 010101

Test: JK Flip Flop - Question 9

An X-Y flip-flop whose characteristic table is given below is to be implemented using a J-K flip-flop

This can be done using-

Detailed Solution for Test: JK Flip Flop - Question 9

Concept:

The characteristic equation of a J-K flip flop is given by-

⇒ Qn+1 = JQ̅n + K̅Qn

Calculation:

Let Qn is the present state and Qn+1 is the next state of the given X-Y flip-flop.

Solving the above using K-map, we get the characteristic equation of X-Y flip-flop is-

Qn+1 = Y̅Q̅n + X̅Qn

Characteristic equation of a J-K flip flop is given by

Qn+1 = JQ̅n + K̅Qn

Comparing, J = Y̅ and K = X

Test: JK Flip Flop - Question 10

A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting ___________

Detailed Solution for Test: JK Flip Flop - Question 10

A J-K flip-flop can be obtained from the clocked S-R flip-flop by augmenting two AND gates.

Test: JK Flip Flop - Question 11

The phenomenon of interpreting unwanted signals on J and K while Cp (clock pulse) is HIGH is called ____

Detailed Solution for Test: JK Flip Flop - Question 11

Ones catching means that the input transitioned to a 1 and back very briefly (unintentionally due to a glitch), but the flip-flop responded and latched it in anyway, i.e., it caught the 1. Similarly for 0’s catching.

Test: JK Flip Flop - Question 12

A J-K flip-flop with J = 1 and K = 1 has a 20 kHz clock input. The Q output is ________

Detailed Solution for Test: JK Flip Flop - Question 12

The flip flop is sensitive only to the positive or negative edge of the clock pulse. So, the flip-flop toggles whenever the clock is falling/rising at edge. This triggering of flip-flop during the transition state, is known as Edge-triggered flip-flop. Thus, the output curve has a time period twice that of the clock. Frequency is inversely related to time period and hence frequency gets halved.

Test: JK Flip Flop - Question 13

Four J-K flip-flops are cascaded with their J-K inputs tied HIGH. If the input frequency (fin) to the first flip-flop is 32 kHz, the output frequency (fout) is ________

Detailed Solution for Test: JK Flip Flop - Question 13

32/2 = 16:-first flip-flop,
16/2 = 8:- second flip-flop,
8/2 = 4:- third flip-flop,
4/2 = 2:- fourth flip-flop.
Since the output frequency is determined on basis of the 4th flip-flop.

Test: JK Flip Flop - Question 14

What is represented by the digital circuit given in the figure below:

Detailed Solution for Test: JK Flip Flop - Question 14

Concept:

In J-K flip-flop, if both the inputs are same then it behaves like T flip-flop.

A T flip-flop is like a JK flip-flop. These are basically a single input version of JK flip-flops. This modified form of JK flip-flop is obtained by connecting both inputs J and K together. It has only one input along with the clock input.

Additional Information
Truth table of T Flip flop

Test: JK Flip Flop - Question 15

How is a J-K flip-flop made to toggle?

Detailed Solution for Test: JK Flip Flop - Question 15

Concept:

The Truth table of JK flip flop is

From the truth table when J = 1, K = 1 the output is reset, i.e. Qn + 1 = Q̅n

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