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Test: Master Slave Flip Flop - Electrical Engineering (EE) MCQ


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15 Questions MCQ Test Analog and Digital Electronics - Test: Master Slave Flip Flop

Test: Master Slave Flip Flop for Electrical Engineering (EE) 2024 is part of Analog and Digital Electronics preparation. The Test: Master Slave Flip Flop questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Master Slave Flip Flop MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Master Slave Flip Flop below.
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Test: Master Slave Flip Flop - Question 1

The asynchronous input can be used to set the flip-flop to the ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 1

The asynchronous input can be used to set the flip-flop to the 1 state or clear the flip-flop to the 0 state at any time, regardless of the condition at the other inputs.

Test: Master Slave Flip Flop - Question 2

D flip-flop is a circuit having ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 2

D flip-flop is a circuit having 4 NAND gates. Two of them are connected with each other.

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Test: Master Slave Flip Flop - Question 3

Master slave flip flop is also referred to as?

Detailed Solution for Test: Master Slave Flip Flop - Question 3

The term pulse triggered means the data is entered on the rising edge of the clock pulse, but the output does not reflect the change until the falling edge of the clock pulse.

Test: Master Slave Flip Flop - Question 4

If one wants to design a binary counter, the preferred type of flip-flop is ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 4

If one wants to design a binary counter, the preferred type of flip-flop is J-K type because it has capability to recover from toggle condition. SR flip-flop is not suitable as it produces the “Invalid State”.

Test: Master Slave Flip Flop - Question 5

Which of the following flip-flops is free from the race around the problem?

Detailed Solution for Test: Master Slave Flip Flop - Question 5

T flip-flop is free from the race around condition because its output depends only on the input; hence there is no any problem creates as like toggle.

Test: Master Slave Flip Flop - Question 6

How many types of triggering take place in a flip flops?

Detailed Solution for Test: Master Slave Flip Flop - Question 6

There are three types of triggering in a flip-flop, viz., level triggering, edge triggering and pulse triggering.

Test: Master Slave Flip Flop - Question 7

The term synchronous means ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 7

The term synchronous means the output changes state only when the clock input is triggered. That is, changes in the output occur in synchronization with the clock.

Test: Master Slave Flip Flop - Question 8

The circuit that generates a spike in response to a momentary change of input signal is called ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 8

The circuit that generates a spike in response to a momentary change of input signal is called R-C differentiator circuit.

Test: Master Slave Flip Flop - Question 9

Input clock of RS flip-flop is given to ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 9

Pulser behaves like an arithmetic operator, to perform the operation or determination of corresponding states.

Test: Master Slave Flip Flop - Question 10

In JK flip flop same input, i.e. at a particular time or during a clock pulse, the output will oscillate back and forth between 0 and 1. At the end of the clock pulse the value of output Q is uncertain. The situation is referred to as?

Detailed Solution for Test: Master Slave Flip Flop - Question 10

A race around condition is a flaw in an electronic system or process whereby the output and result of the process is unexpectedly dependent on the sequence or timing of other events.

Test: Master Slave Flip Flop - Question 11

In a positive edge triggered JK flip flop, a low J and low K produces?

Detailed Solution for Test: Master Slave Flip Flop - Question 11

In JK Flip Flop if J = K = 0 then it holds its current state. There will be no change.

Test: Master Slave Flip Flop - Question 12

S-R type flip-flop can be converted into D type flip-flop if S is connected to R through ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 12

 S-R type flip-flop can be converted into D type flip-flop if S is connected to R through an Inverter gate.

Test: Master Slave Flip Flop - Question 13

Which of the following is the Universal Flip-flop?

Detailed Solution for Test: Master Slave Flip Flop - Question 13

There are lots of flip-flops can be prepared by using J-K flip-flop. So, the name is a universal flip-flop. Also, the JK flip-flop resolves the Forbidden State.

Test: Master Slave Flip Flop - Question 14

Flip-flops are ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 14

Flip-flops are synchronous bistable devices known as bistable multivibrators as they have 2 stable states.

Test: Master Slave Flip Flop - Question 15

The S-R, J-K and D inputs are called ____________

Detailed Solution for Test: Master Slave Flip Flop - Question 15

The S-R, J-K and D inputs are called synchronous inputs because data on these inputs are transferred to the flip-flop’s output only on the triggering edge or level triggering of the clock pulse. Moreover, flip-flops have a clock input whereas latches don’t. Hence, known as synchronous inputs.

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