Test: Shift Registers - 1 - Electrical Engineering (EE) MCQ

The registers in which data can be shifted serially or parallelly are known as shift registers. Based on how binary information is entered or shifted out, shift registers are classified into 4 categories, viz., Serial-In/Serial-Out(SISO), Serial-In/Parallel-Out (SIPO), Parallel-In/Serial-Out (PISO), Parallel-In/Parallel-Out (PIPO).

A shift register can shift it’s data either left or right. The universal shift register is capable of shifting data left, right and parallel load capabilities.

At Preset condition, outputs of flip-flops will be 1. Preset = 1 means Q = 1, thus input is definitely 1.

In Serial-In/Serial-Out shift register, data will be shifted one at a time with every clock pulse. Therefore,
Wait | Store
1100 | 0000
110 | 0000 1^st clock
11 | 0000 2^nd clock.

f = 200 KHZ; T = (1/200) m sec = (1/0.2) micro-sec = 5 micro-sec;
In serial transmission, data enters one bit at a time. After 8 clock cycles only 8 bit will be loaded = 8 * 5 = 40 micro-sec.

SIPO is always known as Serial-in Parallel-out.

Because no other flip-flops are connected with the output Q, therefore one can use the Q out of each FF to take out parallel data.

LSB bit is inverted and feed back to MSB:
01110 → initial
10111 → first clock pulse
01011 → second
00101 → third.

In Serial-In/Parallel-Out shift register, data will be shifted all at a time with every clock pulse. Therefore,
Wait | Store
0111 | 0000
011 | 1000 1^st clk
01 | 1100 2^nd clk
0 | 1110 3^rd clk
X | 1111 4^th clk.

One clock period is = (¹⁄₂) micro-s = 0.5 microseconds. In serial transmission, data enters one bit at a time.
So, the total delay = 0.5 x 8 = 4 micro seconds time is required to transmit information of 8 bits.