Test: Digital Electronics - 4


25 Questions MCQ Test Digital Electronics | Test: Digital Electronics - 4


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This mock test of Test: Digital Electronics - 4 for Electrical Engineering (EE) helps you for every Electrical Engineering (EE) entrance exam. This contains 25 Multiple Choice Questions for Electrical Engineering (EE) Test: Digital Electronics - 4 (mcq) to study with solutions a complete question bank. The solved questions answers in this Test: Digital Electronics - 4 quiz give you a good mix of easy questions and tough questions. Electrical Engineering (EE) students definitely take this Test: Digital Electronics - 4 exercise for a better result in the exam. You can find other Test: Digital Electronics - 4 extra questions, long questions & short questions for Electrical Engineering (EE) on EduRev as well by searching above.
QUESTION: 1

For an N bit ADC, the percentage resolution is [1/2N - 1)] 100.

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QUESTION: 2

Commercial ECL gates use two ground lines and one negative supply to

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QUESTION: 3

Dynamic memory cells are constructed using

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QUESTION: 4

Which of the following is incorrect?

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QUESTION: 5

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q0 Q1 Q2 = 101. The frequency of output Q0 Q1 Q2 will be

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QUESTION: 6

A depletion type NMOS is operated in enhancement mode. Vp = - 4 volts. For VGS = + 3 volts as VDS is increased, ID becomes nearly constant when Vps equals

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QUESTION: 7

A number is expressed in binary 2's complement as 10011 decimal equivalent value is

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QUESTION: 8

Which one of the following is D/A conversion technique?

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QUESTION: 9

Assuming accumulator contain A 64 and the carry is set (1). What will accumulator (A) and carry (CY) contain after ANA A?

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QUESTION: 10

In INHIBIT operation

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QUESTION: 11

A JK flip flop can be converted to D flip flop by

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QUESTION: 12

The product of which of the following gives the figure of merit of a logic family?

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QUESTION: 13

In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

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QUESTION: 14

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.

Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

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QUESTION: 15

A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

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QUESTION: 16

Precisely 1 K byte means

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QUESTION: 17

Data can be changed from spatial code to temporal code and vice-versa by using

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QUESTION: 18

In 8156, the lower times byte is addressed with 24 H, and the upper times byte with

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QUESTION: 19

In the CMOS inverter

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QUESTION: 20

Which of the following is incorrect?

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QUESTION: 21

Which one of the following is used to change data from spatial code to temporal code?

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QUESTION: 22

Which of the following needs DC forward voltage to emit light?

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QUESTION: 23

If a microcomputer has a 64 K memory; what is the hexadecimal notations for the last memory location?

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QUESTION: 24

In the given figure shows a 3 bit shift register using TTL flip flops. Initially all the flip flops are set to 0 state. After 8 clock pulses

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QUESTION: 25

Recommended fanout for ECL is

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