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Test: Digital Electronics - 4 - Electrical Engineering (EE) MCQ


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25 Questions MCQ Test Digital Electronics - Test: Digital Electronics - 4

Test: Digital Electronics - 4 for Electrical Engineering (EE) 2024 is part of Digital Electronics preparation. The Test: Digital Electronics - 4 questions and answers have been prepared according to the Electrical Engineering (EE) exam syllabus.The Test: Digital Electronics - 4 MCQs are made for Electrical Engineering (EE) 2024 Exam. Find important definitions, questions, notes, meanings, examples, exercises, MCQs and online tests for Test: Digital Electronics - 4 below.
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Test: Digital Electronics - 4 - Question 1

For an N bit ADC, the percentage resolution is [1/2N - 1)] 100.

Test: Digital Electronics - 4 - Question 2

Dynamic memory cells are constructed using

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Test: Digital Electronics - 4 - Question 3

Commercial ECL gates use two ground lines and one negative supply to

Test: Digital Electronics - 4 - Question 4

Which of the following is incorrect?

Test: Digital Electronics - 4 - Question 5

A 3 stage Johnson counter (ring) shown in figure is clocked at a constant frequency of fc from the starting state of Q0 Q1 Q2 = 101. The frequency of output Q0 Q1 Q2 will be

Test: Digital Electronics - 4 - Question 6

A depletion type NMOS is operated in enhancement mode. Vp = - 4 volts. For VGS = + 3 volts as VDS is increased, ID becomes nearly constant when Vps equals

Test: Digital Electronics - 4 - Question 7

A number is expressed in binary 2's complement as 10011 decimal equivalent value is

Test: Digital Electronics - 4 - Question 8

Which one of the following is D/A conversion technique?

Test: Digital Electronics - 4 - Question 9

Assuming accumulator contain A 64 and the carry is set (1). What will accumulator (A) and carry (CY) contain after ANA A?

Test: Digital Electronics - 4 - Question 10

In INHIBIT operation

Test: Digital Electronics - 4 - Question 11

The product of which of the following gives the figure of merit of a logic family?

Test: Digital Electronics - 4 - Question 12

A JK flip flop can be converted to D flip flop by

Test: Digital Electronics - 4 - Question 13

In a 4 bit parallel in parallel out shift register A = 1, B = 1, C = 0, D = 1. The data output after 3 clock pulses is

Test: Digital Electronics - 4 - Question 14

Assertion (A): A 4 input variable logic circuit can be implemented using a 8 : 1 multiplexer.

Reason (R): When a multiplexer is used as a logic function generator, the logic design is simple.

Test: Digital Electronics - 4 - Question 15

A 6 MHz channel is used by a digital signalling system initializing four-level signals. The maximum possible transmission rate is

Test: Digital Electronics - 4 - Question 16

Data can be changed from spatial code to temporal code and vice-versa by using

Test: Digital Electronics - 4 - Question 17

Precisely 1 K byte means

Test: Digital Electronics - 4 - Question 18

In 8156, the lower times byte is addressed with 24 H, and the upper times byte with

Test: Digital Electronics - 4 - Question 19

In the CMOS inverter

Test: Digital Electronics - 4 - Question 20

Which of the following is incorrect?

Test: Digital Electronics - 4 - Question 21

Which one of the following is used to change data from spatial code to temporal code?

Test: Digital Electronics - 4 - Question 22

Which of the following needs DC forward voltage to emit light?

Test: Digital Electronics - 4 - Question 23

If a microcomputer has a 64 K memory; what is the hexadecimal notations for the last memory location?

Test: Digital Electronics - 4 - Question 24

In the given figure shows a 3 bit shift register using TTL flip flops. Initially all the flip flops are set to 0 state. After 8 clock pulses

Test: Digital Electronics - 4 - Question 25

Recommended fanout for ECL is

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