Short Notes: ALU and Data Path | Short Notes for Computer Science Engineering - Computer Science Engineering (CSE) PDF Download

 Page 1


The CPU can be divided into a data section and a control section. The data section, 
which is also called the datapath.
Datapath
The registers, the ALU, and the interconnecting bus are collectively referred to as 
the datapath. Each bit in datapath is functionally identical. The datapath is capable 
of performing certain operations on data items.
The control section is basically the control unit, which issues control signals to the 
datapath.
Bus: A Bus is a collection of wires or distinct lines meant to carry data, address and 
control information.
Data Bus: it is used for transmission of data. The number of data lines corresponds 
to the number of bits in a word.
Address Bus: it carries the address of the main memory location from where the 
data can be accessed.
Control Bus: it is used to indicate the direction of data transfer and to coordinate 
the timing of events during the transfer.
PC (Program Counter): Holds the address of the next instruction 
IR (Instruction Register): Holds the executing instruction
Instruction Cache: 'Fast' memory where the next instruction comes from Reg[index]
(Register File): Contains the 32 registers
Arithmetic Logic Unit (ALU): Performs all arithmetic operations
Data Cache: Data read from or written to 'fast' memory
Multiplexer: Multiple inputs selects one output based upon control signal(s)
Single-Cycle Data Path: Each instruction executes in one clock cycle
Multi-Cycle Data Path: Each instruction takes multiple clock cycles
Page 2


The CPU can be divided into a data section and a control section. The data section, 
which is also called the datapath.
Datapath
The registers, the ALU, and the interconnecting bus are collectively referred to as 
the datapath. Each bit in datapath is functionally identical. The datapath is capable 
of performing certain operations on data items.
The control section is basically the control unit, which issues control signals to the 
datapath.
Bus: A Bus is a collection of wires or distinct lines meant to carry data, address and 
control information.
Data Bus: it is used for transmission of data. The number of data lines corresponds 
to the number of bits in a word.
Address Bus: it carries the address of the main memory location from where the 
data can be accessed.
Control Bus: it is used to indicate the direction of data transfer and to coordinate 
the timing of events during the transfer.
PC (Program Counter): Holds the address of the next instruction 
IR (Instruction Register): Holds the executing instruction
Instruction Cache: 'Fast' memory where the next instruction comes from Reg[index]
(Register File): Contains the 32 registers
Arithmetic Logic Unit (ALU): Performs all arithmetic operations
Data Cache: Data read from or written to 'fast' memory
Multiplexer: Multiple inputs selects one output based upon control signal(s)
Single-Cycle Data Path: Each instruction executes in one clock cycle
Multi-Cycle Data Path: Each instruction takes multiple clock cycles
Single-Cycle Data Path:
• Every cycle must be equal length
• The cycle time must be long enough to accommodate the longest instruction. 
Multi-cycle Data Path
• Have the cycle time coincide with the instruction stage time.
• Cycle time = 2 ns (time of longest stage)
• Between stages we need registers to hold data for next stage.
A B
Operation
."16
N S Z 
ALU
• Accumulator: Special register
° One of the inputs to ALU 
° Output of ALU stored back in accumulator
• One-address instructions: Operation and address of one operand
° Other operand and destination is accumulator register 
° AC < - AC op Mem[addr]
° Single address instructions (AC implicit operand)
• Multiple registers: Part of instruction used to choose register operands
1 6
V
1
1 6
Instruction Path
• Program Counter
° Keeps track of program execution 
o Address of next instruction to read from memory 
° May have auto-increment feature or use ALU
• Instruction Register
o Current instruction
° Includes ALU operation and address of operand
Page 3


The CPU can be divided into a data section and a control section. The data section, 
which is also called the datapath.
Datapath
The registers, the ALU, and the interconnecting bus are collectively referred to as 
the datapath. Each bit in datapath is functionally identical. The datapath is capable 
of performing certain operations on data items.
The control section is basically the control unit, which issues control signals to the 
datapath.
Bus: A Bus is a collection of wires or distinct lines meant to carry data, address and 
control information.
Data Bus: it is used for transmission of data. The number of data lines corresponds 
to the number of bits in a word.
Address Bus: it carries the address of the main memory location from where the 
data can be accessed.
Control Bus: it is used to indicate the direction of data transfer and to coordinate 
the timing of events during the transfer.
PC (Program Counter): Holds the address of the next instruction 
IR (Instruction Register): Holds the executing instruction
Instruction Cache: 'Fast' memory where the next instruction comes from Reg[index]
(Register File): Contains the 32 registers
Arithmetic Logic Unit (ALU): Performs all arithmetic operations
Data Cache: Data read from or written to 'fast' memory
Multiplexer: Multiple inputs selects one output based upon control signal(s)
Single-Cycle Data Path: Each instruction executes in one clock cycle
Multi-Cycle Data Path: Each instruction takes multiple clock cycles
Single-Cycle Data Path:
• Every cycle must be equal length
• The cycle time must be long enough to accommodate the longest instruction. 
Multi-cycle Data Path
• Have the cycle time coincide with the instruction stage time.
• Cycle time = 2 ns (time of longest stage)
• Between stages we need registers to hold data for next stage.
A B
Operation
."16
N S Z 
ALU
• Accumulator: Special register
° One of the inputs to ALU 
° Output of ALU stored back in accumulator
• One-address instructions: Operation and address of one operand
° Other operand and destination is accumulator register 
° AC < - AC op Mem[addr]
° Single address instructions (AC implicit operand)
• Multiple registers: Part of instruction used to choose register operands
1 6
V
1
1 6
Instruction Path
• Program Counter
° Keeps track of program execution 
o Address of next instruction to read from memory 
° May have auto-increment feature or use ALU
• Instruction Register
o Current instruction
° Includes ALU operation and address of operand
° Also holds target of jump instruction 
° Immediate operands
• Relationship to Data Path
° PC may be incremented through ALU 
° Contents of IR may also be required as input to ALU
CPU Organisation
it is further classified into three types on the basis of ALU data Paths.
• Stack CPU: In this organisation, ALU operands are required to be in stack and 
all the operations are performed on stack memory, basically, Zero address 
Instruction and One address instructions are used. Example: PUSH A, POP
• Accumulator CPU:ln this organisation, One of the operand is required into the 
main memory and other is required either in register or in memory. After the 
processing, the result will be placed into the main memory. Accumulator 
become the default location here. Example: ADD A
• General Register CPU: In this particular organisation, operands are required 
to be in registers and after the processing, result get stored into the main 
memory. Example: ADD A B , Where A & B are registers.
Bus Configurations in the CPU:
• IOP (Input Output Processor): in this configuration, Different buses are used 
for input otuput devices and memory mapped devices but the control signals 
and address space is common for both of them, this method is quite costly 
as it requires implementation of extra hardware.
• Isolated 10 (10 mapped 10): This configuration uses the common buses and 
common address space for both memory and input output devices but 
different control signal are used for both of them. Here, all the signals are 
active low signal except 1 0, it will work if the value given to the signal is 0.
Control Signal 10/M RD WR
MEMWR 0 1 0
MEMRD 0 0 1
IORD 1 0 1
IOWR 1 1 0
• Memory Mapped 10: In this organisation, the buses and control signals are 
kept common for both memory and input output devices, but the address 
space is divided between them, this is more preferred since no need of
external hardware.
Memory Interface 
Memory
• Separate data and instruction memory: Two address busses, two data busses
• Single combined memory: Single address bus, single data bus
Separate memory
Page 4


The CPU can be divided into a data section and a control section. The data section, 
which is also called the datapath.
Datapath
The registers, the ALU, and the interconnecting bus are collectively referred to as 
the datapath. Each bit in datapath is functionally identical. The datapath is capable 
of performing certain operations on data items.
The control section is basically the control unit, which issues control signals to the 
datapath.
Bus: A Bus is a collection of wires or distinct lines meant to carry data, address and 
control information.
Data Bus: it is used for transmission of data. The number of data lines corresponds 
to the number of bits in a word.
Address Bus: it carries the address of the main memory location from where the 
data can be accessed.
Control Bus: it is used to indicate the direction of data transfer and to coordinate 
the timing of events during the transfer.
PC (Program Counter): Holds the address of the next instruction 
IR (Instruction Register): Holds the executing instruction
Instruction Cache: 'Fast' memory where the next instruction comes from Reg[index]
(Register File): Contains the 32 registers
Arithmetic Logic Unit (ALU): Performs all arithmetic operations
Data Cache: Data read from or written to 'fast' memory
Multiplexer: Multiple inputs selects one output based upon control signal(s)
Single-Cycle Data Path: Each instruction executes in one clock cycle
Multi-Cycle Data Path: Each instruction takes multiple clock cycles
Single-Cycle Data Path:
• Every cycle must be equal length
• The cycle time must be long enough to accommodate the longest instruction. 
Multi-cycle Data Path
• Have the cycle time coincide with the instruction stage time.
• Cycle time = 2 ns (time of longest stage)
• Between stages we need registers to hold data for next stage.
A B
Operation
."16
N S Z 
ALU
• Accumulator: Special register
° One of the inputs to ALU 
° Output of ALU stored back in accumulator
• One-address instructions: Operation and address of one operand
° Other operand and destination is accumulator register 
° AC < - AC op Mem[addr]
° Single address instructions (AC implicit operand)
• Multiple registers: Part of instruction used to choose register operands
1 6
V
1
1 6
Instruction Path
• Program Counter
° Keeps track of program execution 
o Address of next instruction to read from memory 
° May have auto-increment feature or use ALU
• Instruction Register
o Current instruction
° Includes ALU operation and address of operand
° Also holds target of jump instruction 
° Immediate operands
• Relationship to Data Path
° PC may be incremented through ALU 
° Contents of IR may also be required as input to ALU
CPU Organisation
it is further classified into three types on the basis of ALU data Paths.
• Stack CPU: In this organisation, ALU operands are required to be in stack and 
all the operations are performed on stack memory, basically, Zero address 
Instruction and One address instructions are used. Example: PUSH A, POP
• Accumulator CPU:ln this organisation, One of the operand is required into the 
main memory and other is required either in register or in memory. After the 
processing, the result will be placed into the main memory. Accumulator 
become the default location here. Example: ADD A
• General Register CPU: In this particular organisation, operands are required 
to be in registers and after the processing, result get stored into the main 
memory. Example: ADD A B , Where A & B are registers.
Bus Configurations in the CPU:
• IOP (Input Output Processor): in this configuration, Different buses are used 
for input otuput devices and memory mapped devices but the control signals 
and address space is common for both of them, this method is quite costly 
as it requires implementation of extra hardware.
• Isolated 10 (10 mapped 10): This configuration uses the common buses and 
common address space for both memory and input output devices but 
different control signal are used for both of them. Here, all the signals are 
active low signal except 1 0, it will work if the value given to the signal is 0.
Control Signal 10/M RD WR
MEMWR 0 1 0
MEMRD 0 0 1
IORD 1 0 1
IOWR 1 1 0
• Memory Mapped 10: In this organisation, the buses and control signals are 
kept common for both memory and input output devices, but the address 
space is divided between them, this is more preferred since no need of
external hardware.
Memory Interface 
Memory
• Separate data and instruction memory: Two address busses, two data busses
• Single combined memory: Single address bus, single data bus
Separate memory
• ALU output goes to data memory input
• Register input from data memory output
• Data memory address from instruction register
• Instruction register from instruction memory output
• Instruction memory address from program counter
Single memory
• Address from PC or IR
• Memory output to instruction and data registers
• Memory input from ALU output
Memory Interfacing
This concept is used to integrate the CPU and memory unit. Pins are mapped 
between the CPU and main memory to get the required functioning.
Latch is used so that single pins can be used for carrying data as well as address 
i.e, same lines are used to carry data and address.
Memory Accessing Schemes:
• Little Endian Scheme: Data is stored in such a way that lower address 
location contain lower byte and higher address location contain higher byte.
• Big Endian Scheme: Data is stored in such a way that lower address location 
contain higher byte and higher address location contain lower byte.
• The default addressing scheme is Little Endian Scheme.
One-Bus Organization
• CPU registers and the ALU use a single bus to move outgoing and incoming 
data.
• Bus can handle only a single data movement within one clock cycle.
• This bus organization is the simplest and least expensive.
• It limits the amount of data transfer that can be done in the same clock cycle, 
which will slow down the overall performance.
Page 5


The CPU can be divided into a data section and a control section. The data section, 
which is also called the datapath.
Datapath
The registers, the ALU, and the interconnecting bus are collectively referred to as 
the datapath. Each bit in datapath is functionally identical. The datapath is capable 
of performing certain operations on data items.
The control section is basically the control unit, which issues control signals to the 
datapath.
Bus: A Bus is a collection of wires or distinct lines meant to carry data, address and 
control information.
Data Bus: it is used for transmission of data. The number of data lines corresponds 
to the number of bits in a word.
Address Bus: it carries the address of the main memory location from where the 
data can be accessed.
Control Bus: it is used to indicate the direction of data transfer and to coordinate 
the timing of events during the transfer.
PC (Program Counter): Holds the address of the next instruction 
IR (Instruction Register): Holds the executing instruction
Instruction Cache: 'Fast' memory where the next instruction comes from Reg[index]
(Register File): Contains the 32 registers
Arithmetic Logic Unit (ALU): Performs all arithmetic operations
Data Cache: Data read from or written to 'fast' memory
Multiplexer: Multiple inputs selects one output based upon control signal(s)
Single-Cycle Data Path: Each instruction executes in one clock cycle
Multi-Cycle Data Path: Each instruction takes multiple clock cycles
Single-Cycle Data Path:
• Every cycle must be equal length
• The cycle time must be long enough to accommodate the longest instruction. 
Multi-cycle Data Path
• Have the cycle time coincide with the instruction stage time.
• Cycle time = 2 ns (time of longest stage)
• Between stages we need registers to hold data for next stage.
A B
Operation
."16
N S Z 
ALU
• Accumulator: Special register
° One of the inputs to ALU 
° Output of ALU stored back in accumulator
• One-address instructions: Operation and address of one operand
° Other operand and destination is accumulator register 
° AC < - AC op Mem[addr]
° Single address instructions (AC implicit operand)
• Multiple registers: Part of instruction used to choose register operands
1 6
V
1
1 6
Instruction Path
• Program Counter
° Keeps track of program execution 
o Address of next instruction to read from memory 
° May have auto-increment feature or use ALU
• Instruction Register
o Current instruction
° Includes ALU operation and address of operand
° Also holds target of jump instruction 
° Immediate operands
• Relationship to Data Path
° PC may be incremented through ALU 
° Contents of IR may also be required as input to ALU
CPU Organisation
it is further classified into three types on the basis of ALU data Paths.
• Stack CPU: In this organisation, ALU operands are required to be in stack and 
all the operations are performed on stack memory, basically, Zero address 
Instruction and One address instructions are used. Example: PUSH A, POP
• Accumulator CPU:ln this organisation, One of the operand is required into the 
main memory and other is required either in register or in memory. After the 
processing, the result will be placed into the main memory. Accumulator 
become the default location here. Example: ADD A
• General Register CPU: In this particular organisation, operands are required 
to be in registers and after the processing, result get stored into the main 
memory. Example: ADD A B , Where A & B are registers.
Bus Configurations in the CPU:
• IOP (Input Output Processor): in this configuration, Different buses are used 
for input otuput devices and memory mapped devices but the control signals 
and address space is common for both of them, this method is quite costly 
as it requires implementation of extra hardware.
• Isolated 10 (10 mapped 10): This configuration uses the common buses and 
common address space for both memory and input output devices but 
different control signal are used for both of them. Here, all the signals are 
active low signal except 1 0, it will work if the value given to the signal is 0.
Control Signal 10/M RD WR
MEMWR 0 1 0
MEMRD 0 0 1
IORD 1 0 1
IOWR 1 1 0
• Memory Mapped 10: In this organisation, the buses and control signals are 
kept common for both memory and input output devices, but the address 
space is divided between them, this is more preferred since no need of
external hardware.
Memory Interface 
Memory
• Separate data and instruction memory: Two address busses, two data busses
• Single combined memory: Single address bus, single data bus
Separate memory
• ALU output goes to data memory input
• Register input from data memory output
• Data memory address from instruction register
• Instruction register from instruction memory output
• Instruction memory address from program counter
Single memory
• Address from PC or IR
• Memory output to instruction and data registers
• Memory input from ALU output
Memory Interfacing
This concept is used to integrate the CPU and memory unit. Pins are mapped 
between the CPU and main memory to get the required functioning.
Latch is used so that single pins can be used for carrying data as well as address 
i.e, same lines are used to carry data and address.
Memory Accessing Schemes:
• Little Endian Scheme: Data is stored in such a way that lower address 
location contain lower byte and higher address location contain higher byte.
• Big Endian Scheme: Data is stored in such a way that lower address location 
contain higher byte and higher address location contain lower byte.
• The default addressing scheme is Little Endian Scheme.
One-Bus Organization
• CPU registers and the ALU use a single bus to move outgoing and incoming 
data.
• Bus can handle only a single data movement within one clock cycle.
• This bus organization is the simplest and least expensive.
• It limits the amount of data transfer that can be done in the same clock cycle, 
which will slow down the overall performance.
Bus
One-bus datapath
Two-Bus Organization
• General-purpose registers are connected to both buses.
• Data can be transferred from two different registers to the input point of the 
ALU at the same time.
• Two operand operation can fetch both operands in the same clock cycle.
Three-Bus Organization
• Two buses may be used as source buses while the third is used as 
destination.
• The source buses move data out of registers (out-bus), and the destination 
bus may move data into a register (in-bus).
• Each of the two out-buses is connected to an ALU input point. The output of 
the ALU is connected directly to the in-bus
• Increasing the number of buses will also increase the complexity of the 
hardware.
Three Bus Datapath