Short Notes: Machine Instructions and Addressing Modes | Short Notes for Computer Science Engineering - Computer Science Engineering (CSE) PDF Download

 Page 1


 
Computer Instruction
A binary code used for specifying micro operations for computer.
Instruction Code
Group of bits used to instruct the CPU to perform specific operation.
• Instructions are encoded as binary instruction codes.
• Each instruction code contains of a operation code, or opcode, which 
designates the overall purpose of the instruction.
• The number of bits allocated for the opcode determined how many different 
instructions the architecture supports.
Instruction Set 
Collection of instructions.
Instruction Representation
Each instruction has a unique bit pattern, but for human beings a corresponding 
symbolic representation has been defined.
Instruction Cycles
Instruction cycle consists of following phases
• Fetching an instruction from memory.
• Decoding the instruction.
• Reading the effective address from memory in case of the instruction having 
an indirect address.
• Execution of the instruction.
Page 2


 
Computer Instruction
A binary code used for specifying micro operations for computer.
Instruction Code
Group of bits used to instruct the CPU to perform specific operation.
• Instructions are encoded as binary instruction codes.
• Each instruction code contains of a operation code, or opcode, which 
designates the overall purpose of the instruction.
• The number of bits allocated for the opcode determined how many different 
instructions the architecture supports.
Instruction Set 
Collection of instructions.
Instruction Representation
Each instruction has a unique bit pattern, but for human beings a corresponding 
symbolic representation has been defined.
Instruction Cycles
Instruction cycle consists of following phases
• Fetching an instruction from memory.
• Decoding the instruction.
• Reading the effective address from memory in case of the instruction having 
an indirect address.
• Execution of the instruction.
Writing the results back to the memory.
Instruction Format
An instruction consists of bits and these bits are grouped up to make fields.
Some fields in instruction format are as follows
1. Opcode which tells about the operation to be performed.
2. Address field designating a memory address or a processor register.
3. Mode field specifying the way the operand or effective address is determined.
Different types of Instruction formats
Some common types are as: Three address instruction format, Two address 
instruction format, One address instruction format, and Zero address instruction 
format.
• Three Address Instruction Format: This system contains three address fields 
(address of operand- !, address of operand2 and address where result needs to 
be put). The address of next instruction is held in a CPU register called 
Program Counter (PC).
Bits :
Add Result Address OP1 address OP2 address
S 24 24 24
Here, the number of bytes required to encode an instruction is 10 bytes.
Each address requires 24 bit = 3 bytes.
Since, there are three addresses and one opcode field.
Therefore 3 x 3 + 1 =10 bytes.
The number of memory access required is 7 words.
4 words for instruction fetch, 2 words for operand fetch and 1 word for result to
be placed back in memory.
• Two Address Instruction Format: In this format, two addresses and an 
operation field is there. The result is stored in either of the operand address
i.e., either in address of first operand or in the address of second operand. 
CPU register called Program Counter (PC) contains the address of next 
instruction. •
Op Code
Add Result Address OP1 address
S 24 24
• One Address Instruction Format: One address field and an operation field. 
This address is of the first operand. The second operand and the result are 
stored in a CPU register called Accumulator Register (AR). Since, a machine 
has only one accumulator, it needs not be explicitly mentioned in the 
instruction. A CPU register (i.e., Program Counter (PC) holds the address of 
next instruction. In this scenario, two extra instructions are required to load 
and store the accumulator contents.
Page 3


 
Computer Instruction
A binary code used for specifying micro operations for computer.
Instruction Code
Group of bits used to instruct the CPU to perform specific operation.
• Instructions are encoded as binary instruction codes.
• Each instruction code contains of a operation code, or opcode, which 
designates the overall purpose of the instruction.
• The number of bits allocated for the opcode determined how many different 
instructions the architecture supports.
Instruction Set 
Collection of instructions.
Instruction Representation
Each instruction has a unique bit pattern, but for human beings a corresponding 
symbolic representation has been defined.
Instruction Cycles
Instruction cycle consists of following phases
• Fetching an instruction from memory.
• Decoding the instruction.
• Reading the effective address from memory in case of the instruction having 
an indirect address.
• Execution of the instruction.
Writing the results back to the memory.
Instruction Format
An instruction consists of bits and these bits are grouped up to make fields.
Some fields in instruction format are as follows
1. Opcode which tells about the operation to be performed.
2. Address field designating a memory address or a processor register.
3. Mode field specifying the way the operand or effective address is determined.
Different types of Instruction formats
Some common types are as: Three address instruction format, Two address 
instruction format, One address instruction format, and Zero address instruction 
format.
• Three Address Instruction Format: This system contains three address fields 
(address of operand- !, address of operand2 and address where result needs to 
be put). The address of next instruction is held in a CPU register called 
Program Counter (PC).
Bits :
Add Result Address OP1 address OP2 address
S 24 24 24
Here, the number of bytes required to encode an instruction is 10 bytes.
Each address requires 24 bit = 3 bytes.
Since, there are three addresses and one opcode field.
Therefore 3 x 3 + 1 =10 bytes.
The number of memory access required is 7 words.
4 words for instruction fetch, 2 words for operand fetch and 1 word for result to
be placed back in memory.
• Two Address Instruction Format: In this format, two addresses and an 
operation field is there. The result is stored in either of the operand address
i.e., either in address of first operand or in the address of second operand. 
CPU register called Program Counter (PC) contains the address of next 
instruction. •
Op Code
Add Result Address OP1 address
S 24 24
• One Address Instruction Format: One address field and an operation field. 
This address is of the first operand. The second operand and the result are 
stored in a CPU register called Accumulator Register (AR). Since, a machine 
has only one accumulator, it needs not be explicitly mentioned in the 
instruction. A CPU register (i.e., Program Counter (PC) holds the address of 
next instruction. In this scenario, two extra instructions are required to load 
and store the accumulator contents.
Op Code
Add OP1 address
S 24
Number of bits required to encode an instruction is 4 bytes, i.e., each address 
requires 24 bits = 3 bytes. Since, there are one address and one operation code 
field, 1* 3 + 1= 4 bytes.
The number of memory access required is 3 words i.e., 2 words for instruction 
fetch +1 word for code for operand fetch.
• Zero Address Instruction Format: Stack is included in the CPU for performing 
arithmetic and logic instructions with no addresses. The operands are pushed 
onto the stack from memory and ALU operations are implicitly performed on 
the top elements of the stack. The address of the next instruction is held in a 
CPU register called program counter.
Op Code
Bits
Add
S
e.g., Add
Top of stack <- Top of stack + second top of stack.
Addressing Modes
The different ways in which the location of an operand is specified in an instruction 
are referred to as addressing modes.
Types of Addressing Modes 
Memory Based Addressing Modes:
• Implied Addressing Mode: In this mode the operands are specified implicitly 
in the definition of an instruction.
• Immediate Addressing Mode: In this mode the operand is specified in the 
instruction itself or we can say that, an immediate mode instruction has an 
operand rather than an address.
• Direct Register Addressing Mode: In this mode, One of the operand is in 
registers and other is taken from mempry.
• Direct Addressing Mode: It this mode, the address of the memory location 
that holds the operand is included in the instruction. The effective address is 
the address part of the instruction.
• Indirect Addressing Mode: In this mode the address field of the instruction 
gives the address where the effective address is stored in memory.
• Relative Addressing Mode: In this mode the content of program counter is 
added to the address part of the instruction to calculate the effective address.
• Indexed Addressing Mode: In this mode, the effective address will be 
calculated as the addition of the content of index register and the address 
part of the instruction.
Transfer Of Control Addressing Modes:
PC Relative Addressing Mode: This addressing mode is used to access the 
instruction within the segment, therefore only one offset address is required.
Page 4


 
Computer Instruction
A binary code used for specifying micro operations for computer.
Instruction Code
Group of bits used to instruct the CPU to perform specific operation.
• Instructions are encoded as binary instruction codes.
• Each instruction code contains of a operation code, or opcode, which 
designates the overall purpose of the instruction.
• The number of bits allocated for the opcode determined how many different 
instructions the architecture supports.
Instruction Set 
Collection of instructions.
Instruction Representation
Each instruction has a unique bit pattern, but for human beings a corresponding 
symbolic representation has been defined.
Instruction Cycles
Instruction cycle consists of following phases
• Fetching an instruction from memory.
• Decoding the instruction.
• Reading the effective address from memory in case of the instruction having 
an indirect address.
• Execution of the instruction.
Writing the results back to the memory.
Instruction Format
An instruction consists of bits and these bits are grouped up to make fields.
Some fields in instruction format are as follows
1. Opcode which tells about the operation to be performed.
2. Address field designating a memory address or a processor register.
3. Mode field specifying the way the operand or effective address is determined.
Different types of Instruction formats
Some common types are as: Three address instruction format, Two address 
instruction format, One address instruction format, and Zero address instruction 
format.
• Three Address Instruction Format: This system contains three address fields 
(address of operand- !, address of operand2 and address where result needs to 
be put). The address of next instruction is held in a CPU register called 
Program Counter (PC).
Bits :
Add Result Address OP1 address OP2 address
S 24 24 24
Here, the number of bytes required to encode an instruction is 10 bytes.
Each address requires 24 bit = 3 bytes.
Since, there are three addresses and one opcode field.
Therefore 3 x 3 + 1 =10 bytes.
The number of memory access required is 7 words.
4 words for instruction fetch, 2 words for operand fetch and 1 word for result to
be placed back in memory.
• Two Address Instruction Format: In this format, two addresses and an 
operation field is there. The result is stored in either of the operand address
i.e., either in address of first operand or in the address of second operand. 
CPU register called Program Counter (PC) contains the address of next 
instruction. •
Op Code
Add Result Address OP1 address
S 24 24
• One Address Instruction Format: One address field and an operation field. 
This address is of the first operand. The second operand and the result are 
stored in a CPU register called Accumulator Register (AR). Since, a machine 
has only one accumulator, it needs not be explicitly mentioned in the 
instruction. A CPU register (i.e., Program Counter (PC) holds the address of 
next instruction. In this scenario, two extra instructions are required to load 
and store the accumulator contents.
Op Code
Add OP1 address
S 24
Number of bits required to encode an instruction is 4 bytes, i.e., each address 
requires 24 bits = 3 bytes. Since, there are one address and one operation code 
field, 1* 3 + 1= 4 bytes.
The number of memory access required is 3 words i.e., 2 words for instruction 
fetch +1 word for code for operand fetch.
• Zero Address Instruction Format: Stack is included in the CPU for performing 
arithmetic and logic instructions with no addresses. The operands are pushed 
onto the stack from memory and ALU operations are implicitly performed on 
the top elements of the stack. The address of the next instruction is held in a 
CPU register called program counter.
Op Code
Bits
Add
S
e.g., Add
Top of stack <- Top of stack + second top of stack.
Addressing Modes
The different ways in which the location of an operand is specified in an instruction 
are referred to as addressing modes.
Types of Addressing Modes 
Memory Based Addressing Modes:
• Implied Addressing Mode: In this mode the operands are specified implicitly 
in the definition of an instruction.
• Immediate Addressing Mode: In this mode the operand is specified in the 
instruction itself or we can say that, an immediate mode instruction has an 
operand rather than an address.
• Direct Register Addressing Mode: In this mode, One of the operand is in 
registers and other is taken from mempry.
• Direct Addressing Mode: It this mode, the address of the memory location 
that holds the operand is included in the instruction. The effective address is 
the address part of the instruction.
• Indirect Addressing Mode: In this mode the address field of the instruction 
gives the address where the effective address is stored in memory.
• Relative Addressing Mode: In this mode the content of program counter is 
added to the address part of the instruction to calculate the effective address.
• Indexed Addressing Mode: In this mode, the effective address will be 
calculated as the addition of the content of index register and the address 
part of the instruction.
Transfer Of Control Addressing Modes:
PC Relative Addressing Mode: This addressing mode is used to access the 
instruction within the segment, therefore only one offset address is required.
• Base register Addressing Mode: This addressing mode is used to access the 
instructions between two segments, therfore, base address as well as offset 
is required.
Types of Instructions
• Data Transfer Instructions: Data transfer instructions cause transfer of data 
from one location to another without changing the information content. The 
common transfers may be between memory and processor registers, between 
processor registers and input/output.
Typical Data Transfer Instructions
Name Mnemonic
LOAD LD
STORE ST
MOVE MOV
EXCHANGE XCH
INPUT IN
OUTPUT OUT
PUSH PUSH
POP POP
• Data Manipulation Instructions: Data manipulation instructions perform 
operations on data and provide the computational capabilities for the 
computer. There are three types of data manipulation instructions: Arithmetic 
instructions, Logical and bit manipulation instructions, and Shift instructions.
Typical Arithmetic Instructions
Name Mnemonic
INCREMENT INC
DECREMENT DEC
ADD ADD
SUBTRACT SUB
MULTIPLY MUL
DIVIDE DIV
ADD WITH CARRY ADDC
SUBTRACT WITH BORROW7 SUBB
NEGATIVE NEG
Typical Logical and Bit Manipulation Instructions
Page 5


 
Computer Instruction
A binary code used for specifying micro operations for computer.
Instruction Code
Group of bits used to instruct the CPU to perform specific operation.
• Instructions are encoded as binary instruction codes.
• Each instruction code contains of a operation code, or opcode, which 
designates the overall purpose of the instruction.
• The number of bits allocated for the opcode determined how many different 
instructions the architecture supports.
Instruction Set 
Collection of instructions.
Instruction Representation
Each instruction has a unique bit pattern, but for human beings a corresponding 
symbolic representation has been defined.
Instruction Cycles
Instruction cycle consists of following phases
• Fetching an instruction from memory.
• Decoding the instruction.
• Reading the effective address from memory in case of the instruction having 
an indirect address.
• Execution of the instruction.
Writing the results back to the memory.
Instruction Format
An instruction consists of bits and these bits are grouped up to make fields.
Some fields in instruction format are as follows
1. Opcode which tells about the operation to be performed.
2. Address field designating a memory address or a processor register.
3. Mode field specifying the way the operand or effective address is determined.
Different types of Instruction formats
Some common types are as: Three address instruction format, Two address 
instruction format, One address instruction format, and Zero address instruction 
format.
• Three Address Instruction Format: This system contains three address fields 
(address of operand- !, address of operand2 and address where result needs to 
be put). The address of next instruction is held in a CPU register called 
Program Counter (PC).
Bits :
Add Result Address OP1 address OP2 address
S 24 24 24
Here, the number of bytes required to encode an instruction is 10 bytes.
Each address requires 24 bit = 3 bytes.
Since, there are three addresses and one opcode field.
Therefore 3 x 3 + 1 =10 bytes.
The number of memory access required is 7 words.
4 words for instruction fetch, 2 words for operand fetch and 1 word for result to
be placed back in memory.
• Two Address Instruction Format: In this format, two addresses and an 
operation field is there. The result is stored in either of the operand address
i.e., either in address of first operand or in the address of second operand. 
CPU register called Program Counter (PC) contains the address of next 
instruction. •
Op Code
Add Result Address OP1 address
S 24 24
• One Address Instruction Format: One address field and an operation field. 
This address is of the first operand. The second operand and the result are 
stored in a CPU register called Accumulator Register (AR). Since, a machine 
has only one accumulator, it needs not be explicitly mentioned in the 
instruction. A CPU register (i.e., Program Counter (PC) holds the address of 
next instruction. In this scenario, two extra instructions are required to load 
and store the accumulator contents.
Op Code
Add OP1 address
S 24
Number of bits required to encode an instruction is 4 bytes, i.e., each address 
requires 24 bits = 3 bytes. Since, there are one address and one operation code 
field, 1* 3 + 1= 4 bytes.
The number of memory access required is 3 words i.e., 2 words for instruction 
fetch +1 word for code for operand fetch.
• Zero Address Instruction Format: Stack is included in the CPU for performing 
arithmetic and logic instructions with no addresses. The operands are pushed 
onto the stack from memory and ALU operations are implicitly performed on 
the top elements of the stack. The address of the next instruction is held in a 
CPU register called program counter.
Op Code
Bits
Add
S
e.g., Add
Top of stack <- Top of stack + second top of stack.
Addressing Modes
The different ways in which the location of an operand is specified in an instruction 
are referred to as addressing modes.
Types of Addressing Modes 
Memory Based Addressing Modes:
• Implied Addressing Mode: In this mode the operands are specified implicitly 
in the definition of an instruction.
• Immediate Addressing Mode: In this mode the operand is specified in the 
instruction itself or we can say that, an immediate mode instruction has an 
operand rather than an address.
• Direct Register Addressing Mode: In this mode, One of the operand is in 
registers and other is taken from mempry.
• Direct Addressing Mode: It this mode, the address of the memory location 
that holds the operand is included in the instruction. The effective address is 
the address part of the instruction.
• Indirect Addressing Mode: In this mode the address field of the instruction 
gives the address where the effective address is stored in memory.
• Relative Addressing Mode: In this mode the content of program counter is 
added to the address part of the instruction to calculate the effective address.
• Indexed Addressing Mode: In this mode, the effective address will be 
calculated as the addition of the content of index register and the address 
part of the instruction.
Transfer Of Control Addressing Modes:
PC Relative Addressing Mode: This addressing mode is used to access the 
instruction within the segment, therefore only one offset address is required.
• Base register Addressing Mode: This addressing mode is used to access the 
instructions between two segments, therfore, base address as well as offset 
is required.
Types of Instructions
• Data Transfer Instructions: Data transfer instructions cause transfer of data 
from one location to another without changing the information content. The 
common transfers may be between memory and processor registers, between 
processor registers and input/output.
Typical Data Transfer Instructions
Name Mnemonic
LOAD LD
STORE ST
MOVE MOV
EXCHANGE XCH
INPUT IN
OUTPUT OUT
PUSH PUSH
POP POP
• Data Manipulation Instructions: Data manipulation instructions perform 
operations on data and provide the computational capabilities for the 
computer. There are three types of data manipulation instructions: Arithmetic 
instructions, Logical and bit manipulation instructions, and Shift instructions.
Typical Arithmetic Instructions
Name Mnemonic
INCREMENT INC
DECREMENT DEC
ADD ADD
SUBTRACT SUB
MULTIPLY MUL
DIVIDE DIV
ADD WITH CARRY ADDC
SUBTRACT WITH BORROW7 SUBB
NEGATIVE NEG
Typical Logical and Bit Manipulation Instructions
bailie Mnemonic
CLEAR CLR
COMPLEMENT COM
AND AND
OR OR
EXCLUSIVE OR XOR
CLEAR CARRY CLRC
SET CARRY SETC
COMPLEMENT CARRY COMC
ENABLE INTERRUPT El
DISABLE INTERRUPT DI
Typical Shift Instructions
Name Mnemonic
LOGICAL SHIFT RIGHT SHR
LOGICAL SHIFT LEFT SHL
ROTATE RIGHT ROR
ROTATE LEFT ROL
Program Control Instructions
Program control instructions specify conditions for altering the content of the 
program counter, while data transfer and manipulation instructions specify 
conditions for data processing operations. The change in value of a program 
counter as a result of the execution of a program control instruction causes a break 
in the sequence of instruction execution.
Typical Program Control Instructions
Name Mnemonic
BRANCH BR
JUMP JMP
SKIP SKP
CALL CALL
RETURN RET
COMPARE CMP
TEST TST
Program Interrupt
The program interrupts are used to handle a variety of problems that arise out of 
normal program sequence.
• Program interrupts are used to transfer the program control from a currently 
running program to another service program as a result of an external or 
internal generated request. Control returns to the original program after the 
service program is executed.
Types of Interrupts
Interrupts can be classified into two categories:
On the basis of Masking