Short Notes: Sequential Circuit | Short Notes for Computer Science Engineering - Computer Science Engineering (CSE) PDF Download

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D Flip-Flop 
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S 
input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock 
pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the 
clear state.  
 
(a) Logic diagram with NAND gates  
(b) Graphical symbol  (c) Transition table  
  
Figure 5. Clocked D flip-flop  
 JK Flip-Flop 
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. 
Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set 
and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its 
complement state, ie., if Q=1, it switches to Q=0 and vice versa.  
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared 
during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop 
is set with a clock pulse only if Q' was previously 1.  
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the 
outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the 
clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse 
width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T 
flip-flop presented next.  
 
(a) Logic diagram  
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D Flip-Flop 
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S 
input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock 
pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the 
clear state.  
 
(a) Logic diagram with NAND gates  
(b) Graphical symbol  (c) Transition table  
  
Figure 5. Clocked D flip-flop  
 JK Flip-Flop 
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. 
Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set 
and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its 
complement state, ie., if Q=1, it switches to Q=0 and vice versa.  
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared 
during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop 
is set with a clock pulse only if Q' was previously 1.  
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the 
outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the 
clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse 
width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T 
flip-flop presented next.  
 
(a) Logic diagram  
                                                               
 
 
(c) Transition table  
Figure 6. Clocked JK flip-flop  
T Flip-Flop 
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is obtained from the JK 
type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse.  
 
(a) Logic diagram  
 
(b) Graphical symbol  
 
(c) Transition table  
Triggering of Flip-flops 
The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the 
transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and Figure 3 require an input trigger 
defined by a change in signal level. This level must be returned to its initial level before a second trigger is applied. 
Clocked flip-flops are triggered by pulses.  
The feedback path between the combinational circuit and memory elements in Figure 1 can produce instability if the 
outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the 
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D Flip-Flop 
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S 
input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock 
pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the 
clear state.  
 
(a) Logic diagram with NAND gates  
(b) Graphical symbol  (c) Transition table  
  
Figure 5. Clocked D flip-flop  
 JK Flip-Flop 
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. 
Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set 
and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its 
complement state, ie., if Q=1, it switches to Q=0 and vice versa.  
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared 
during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop 
is set with a clock pulse only if Q' was previously 1.  
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the 
outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the 
clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse 
width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T 
flip-flop presented next.  
 
(a) Logic diagram  
                                                               
 
 
(c) Transition table  
Figure 6. Clocked JK flip-flop  
T Flip-Flop 
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is obtained from the JK 
type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse.  
 
(a) Logic diagram  
 
(b) Graphical symbol  
 
(c) Transition table  
Triggering of Flip-flops 
The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the 
transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and Figure 3 require an input trigger 
defined by a change in signal level. This level must be returned to its initial level before a second trigger is applied. 
Clocked flip-flops are triggered by pulses.  
The feedback path between the combinational circuit and memory elements in Figure 1 can produce instability if the 
outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the 
                                                               
 
flip-flop inputs are being sampled by the clock pulse. A way to solve the feedback timing problem is to make the flip-
flop sensitive to the pulse transition rather than the pulse duration.  
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in Figure 8 the 
positive transition is defined as the positive edge and the negative transition as the negative edge.  
 
Figure 8. Definition of clock pulse transition  
The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the state transition 
starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the clock is still 1, a new output 
state may occur. If the flip-flop is made to respond to the positive (or negative) edge transition only, instead of the entire 
pulse duration, then the multiple-transition problem can be eliminated.  
Master-Slave Flip-Flop 
A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a 
slave. The logic diagram of an SR flip-flop is shown in Figure 9. The master flip-flop is enabled on the positive edge of 
the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is 
transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is 
enabled. The slave flip-flop then goes to the same state as the master flip-flop.  
 
Figure 9. Logic diagram of a master-slave flip-flop  
 
Master slave RS flip flop  
The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in the clear state prior to the 
occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock 
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D Flip-Flop 
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S 
input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock 
pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the 
clear state.  
 
(a) Logic diagram with NAND gates  
(b) Graphical symbol  (c) Transition table  
  
Figure 5. Clocked D flip-flop  
 JK Flip-Flop 
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. 
Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set 
and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its 
complement state, ie., if Q=1, it switches to Q=0 and vice versa.  
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared 
during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop 
is set with a clock pulse only if Q' was previously 1.  
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the 
outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the 
clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse 
width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T 
flip-flop presented next.  
 
(a) Logic diagram  
                                                               
 
 
(c) Transition table  
Figure 6. Clocked JK flip-flop  
T Flip-Flop 
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is obtained from the JK 
type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse.  
 
(a) Logic diagram  
 
(b) Graphical symbol  
 
(c) Transition table  
Triggering of Flip-flops 
The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the 
transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and Figure 3 require an input trigger 
defined by a change in signal level. This level must be returned to its initial level before a second trigger is applied. 
Clocked flip-flops are triggered by pulses.  
The feedback path between the combinational circuit and memory elements in Figure 1 can produce instability if the 
outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the 
                                                               
 
flip-flop inputs are being sampled by the clock pulse. A way to solve the feedback timing problem is to make the flip-
flop sensitive to the pulse transition rather than the pulse duration.  
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in Figure 8 the 
positive transition is defined as the positive edge and the negative transition as the negative edge.  
 
Figure 8. Definition of clock pulse transition  
The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the state transition 
starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the clock is still 1, a new output 
state may occur. If the flip-flop is made to respond to the positive (or negative) edge transition only, instead of the entire 
pulse duration, then the multiple-transition problem can be eliminated.  
Master-Slave Flip-Flop 
A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a 
slave. The logic diagram of an SR flip-flop is shown in Figure 9. The master flip-flop is enabled on the positive edge of 
the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is 
transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is 
enabled. The slave flip-flop then goes to the same state as the master flip-flop.  
 
Figure 9. Logic diagram of a master-slave flip-flop  
 
Master slave RS flip flop  
The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in the clear state prior to the 
occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock 
                                                               
 
pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an 
additional inverter between the CP terminal and the input of the master.  
 
Figure 10. Timing relationship in a master slave flip-flop  
Edge Triggered Flip-Flop 
Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-triggered flip-
flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not 
affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered 
flip-flops cause a transition on the positive edge of the clock pulse (positive-edge-triggered), and others on the negative 
edge of the pulse (negative-edge-triggered). The logic diagram of a D-type positive-edge-triggered flip-flop is shown in 
Figure 11.  
 
Figure 11. D-type positive-edge triggered flip-flop 
When using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs make their 
transitions at the same time, ie., during either the negative edge or the positive edge of the clock pulse.  
Direct Inputs 
Flip-flops in IC packages sometimes provide special inputs for setting or clearing the flip-flop asynchronously. They are 
usually called preset and clear. They affect the flip-flop without the need for a clock pulse. These inputs are useful for 
bringing flip-flops to an intial state before their clocked operation. For example, after power is turned on in a digital 
system, the states of the flip-flops are indeterminate. Activating the clear input clears all the flip-flops to an initial state 
of 0. The graphic symbol of a JK flip-flop with an active-low clear is shown in Figure 12.  
 
(a) Graphic Symbol  
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D Flip-Flop 
The D flip-flop shown in Figure 5 is a modification of the clocked SR flip-flop. The D input goes directly into the S 
input and the complement of the D input goes to the R input. The D input is sampled during the occurrence of a clock 
pulse. If it is 1, the flip-flop is switched to the set state (unless it was already set). If it is 0, the flip-flop switches to the 
clear state.  
 
(a) Logic diagram with NAND gates  
(b) Graphical symbol  (c) Transition table  
  
Figure 5. Clocked D flip-flop  
 JK Flip-Flop 
A JK flip-flop is a refinement of the SR flip-flop in that the indeterminate state of the SR type is defined in the JK type. 
Inputs J and K behave like inputs S and R to set and clear the flip-flop (note that in a JK flip-flop, the letter J is for set 
and the letter K is for clear). When logic 1 inputs are applied to both J and K simultaneously, the flip-flop switches to its 
complement state, ie., if Q=1, it switches to Q=0 and vice versa.  
A clocked JK flip-flop is shown in Figure 6. Output Q is ANDed with K and CP inputs so that the flip-flop is cleared 
during a clock pulse only if Q was previously 1. Similarly, ouput Q' is ANDed with J and CP inputs so that the flip-flop 
is set with a clock pulse only if Q' was previously 1.  
Note that because of the feedback connection in the JK flip-flop, a CP signal which remains a 1 (while J=K=1) after the 
outputs have been complemented once will cause repeated and continuous transitions of the outputs. To avoid this, the 
clock pulses must have a time duration less than the propagation delay through the flip-flop. The restriction on the pulse 
width can be eliminated with a master-slave or edge-triggered construction. The same reasoning also applies to the T 
flip-flop presented next.  
 
(a) Logic diagram  
                                                               
 
 
(c) Transition table  
Figure 6. Clocked JK flip-flop  
T Flip-Flop 
The T flip-flop is a single input version of the JK flip-flop. As shown in Figure 7, the T flip-flop is obtained from the JK 
type if both inputs are tied together. The output of the T flip-flop "toggles" with each clock pulse.  
 
(a) Logic diagram  
 
(b) Graphical symbol  
 
(c) Transition table  
Triggering of Flip-flops 
The state of a flip-flop is changed by a momentary change in the input signal. This change is called a trigger and the 
transition it causes is said to trigger the flip-flop. The basic circuits of Figure 2 and Figure 3 require an input trigger 
defined by a change in signal level. This level must be returned to its initial level before a second trigger is applied. 
Clocked flip-flops are triggered by pulses.  
The feedback path between the combinational circuit and memory elements in Figure 1 can produce instability if the 
outputs of the memory elements (flip-flops) are changing while the outputs of the combinational circuit that go to the 
                                                               
 
flip-flop inputs are being sampled by the clock pulse. A way to solve the feedback timing problem is to make the flip-
flop sensitive to the pulse transition rather than the pulse duration.  
The clock pulse goes through two signal transitions: from 0 to 1 and the return from 1 to 0. As shown in Figure 8 the 
positive transition is defined as the positive edge and the negative transition as the negative edge.  
 
Figure 8. Definition of clock pulse transition  
The clocked flip-flops already introduced are triggered during the positive edge of the pulse, and the state transition 
starts as soon as the pulse reaches the logic-1 level. If the other inputs change while the clock is still 1, a new output 
state may occur. If the flip-flop is made to respond to the positive (or negative) edge transition only, instead of the entire 
pulse duration, then the multiple-transition problem can be eliminated.  
Master-Slave Flip-Flop 
A master-slave flip-flop is constructed from two seperate flip-flops. One circuit serves as a master and the other as a 
slave. The logic diagram of an SR flip-flop is shown in Figure 9. The master flip-flop is enabled on the positive edge of 
the clock pulse CP and the slave flip-flop is disabled by the inverter. The information at the external R and S inputs is 
transmitted to the master flip-flop. When the pulse returns to 0, the master flip-flop is disabled and the slave flip-flop is 
enabled. The slave flip-flop then goes to the same state as the master flip-flop.  
 
Figure 9. Logic diagram of a master-slave flip-flop  
 
Master slave RS flip flop  
The timing relationship is shown in Figure 10 and is assumed that the flip-flop is in the clear state prior to the 
occurrence of the clock pulse. The output state of the master-slave flip-flop occurs on the negative transition of the clock 
                                                               
 
pulse. Some master-slave flip-flops change output state on the positive transition of the clock pulse by having an 
additional inverter between the CP terminal and the input of the master.  
 
Figure 10. Timing relationship in a master slave flip-flop  
Edge Triggered Flip-Flop 
Another type of flip-flop that synchronizes the state changes during a clock pulse transition is the edge-triggered flip-
flop. When the clock pulse input exceeds a specific threshold level, the inputs are locked out and the flip-flop is not 
affected by further changes in the inputs until the clock pulse returns to 0 and another pulse occurs. Some edge-triggered 
flip-flops cause a transition on the positive edge of the clock pulse (positive-edge-triggered), and others on the negative 
edge of the pulse (negative-edge-triggered). The logic diagram of a D-type positive-edge-triggered flip-flop is shown in 
Figure 11.  
 
Figure 11. D-type positive-edge triggered flip-flop 
When using different types of flip-flops in the same circuit, one must ensure that all flip-flop outputs make their 
transitions at the same time, ie., during either the negative edge or the positive edge of the clock pulse.  
Direct Inputs 
Flip-flops in IC packages sometimes provide special inputs for setting or clearing the flip-flop asynchronously. They are 
usually called preset and clear. They affect the flip-flop without the need for a clock pulse. These inputs are useful for 
bringing flip-flops to an intial state before their clocked operation. For example, after power is turned on in a digital 
system, the states of the flip-flops are indeterminate. Activating the clear input clears all the flip-flops to an initial state 
of 0. The graphic symbol of a JK flip-flop with an active-low clear is shown in Figure 12.  
 
(a) Graphic Symbol  
                                                               
 
 
(b) Transition table  
Figure 12. JK flip-flop with direct clear  
 Summary 
Since memory elements in sequential circuits are usually flip-flops, it is worth summarising the behaviour of various 
flip-flop types before proceeding further. All flip-flops can be divided into four basic types: SR, JK, D and T. They 
differ in the number of inputs and in the response invoked by different value of input signals. The four types of flip-
flops are defined in Table 1. 
Table 1. Flip-flop Types 
TYPE 
FLIP-FLOP 
SYMBOL 
CHARACTERISTIC 
TABLE 
CHARACTERISTIC 
EQUATION 
EXCITATION TABLE 
SR 
 
S R Q(next) 
0 0 Q 
0 1 0 
1 0 1 
1 1 ? 
 
Q(next) = S + R'Q  
SR = 0 
Q Q(next) S R 
0 0 0 X 
0 1 1 0 
1 0 0 1 
1 1 X 0 
 
JK 
 
J K Q(next) 
0 0 Q 
0 1 0 
1 0 1 
1 1 Q' 
 
Q(next) = JQ' + K'Q 
Q Q(next) J K 
0 0 0 X 
0 1 1 X 
1 0 X 1 
1 1 X 0 
 
D 
 
D Q(next) 
0 0 
1 1 
 
Q(next) = D 
Q Q(next) D 
0 0 0 
0 1 1 
1 0 0 
1 1 1 
 
T 
 
T Q(next) 
0 Q 
1 Q' 
 
Q(next) = TQ' + T'Q 
Q Q(next) T 
0 0 0 
0 1 1 
1 0 1 
1 1 0