Test Fixtures

 Page 1


Test Fixtures 
•? Provides clock 
•? Provides test vectors/checks results 
–? test vectors and results are precomputed 
–? usually read vectors from file 
•? Models system environment 
–? Complex program that simulates external environment 
•? Test fixture can all the language features 
–? initial, delays, read/write files, etc. 
Simulation 
Test Fixture 
(Specification) 
Circuit Description 
(Synthesizeable) 
Page 2


Test Fixtures 
•? Provides clock 
•? Provides test vectors/checks results 
–? test vectors and results are precomputed 
–? usually read vectors from file 
•? Models system environment 
–? Complex program that simulates external environment 
•? Test fixture can all the language features 
–? initial, delays, read/write files, etc. 
Simulation 
Test Fixture 
(Specification) 
Circuit Description 
(Synthesizeable) 
Test Fixtures 
Verilog programs used to drive the simulation 
Much easier than drawing waveforms 
Test fixtures are usually non-synthesizeable 
Anything goes!   Really is like writing a C program 
Not really Verilog! 
Self-checking text fixtures are required for regression testing 
You can write an arbitrary program in Verilog 
Page 3


Test Fixtures 
•? Provides clock 
•? Provides test vectors/checks results 
–? test vectors and results are precomputed 
–? usually read vectors from file 
•? Models system environment 
–? Complex program that simulates external environment 
•? Test fixture can all the language features 
–? initial, delays, read/write files, etc. 
Simulation 
Test Fixture 
(Specification) 
Circuit Description 
(Synthesizeable) 
Test Fixtures 
Verilog programs used to drive the simulation 
Much easier than drawing waveforms 
Test fixtures are usually non-synthesizeable 
Anything goes!   Really is like writing a C program 
Not really Verilog! 
Self-checking text fixtures are required for regression testing 
You can write an arbitrary program in Verilog 
Initial Blocks 
•? Like always blocks 
–? execute once at the very beginning of simulation 
–? not synthesizeable 
•? use reset instead 
Page 4


Test Fixtures 
•? Provides clock 
•? Provides test vectors/checks results 
–? test vectors and results are precomputed 
–? usually read vectors from file 
•? Models system environment 
–? Complex program that simulates external environment 
•? Test fixture can all the language features 
–? initial, delays, read/write files, etc. 
Simulation 
Test Fixture 
(Specification) 
Circuit Description 
(Synthesizeable) 
Test Fixtures 
Verilog programs used to drive the simulation 
Much easier than drawing waveforms 
Test fixtures are usually non-synthesizeable 
Anything goes!   Really is like writing a C program 
Not really Verilog! 
Self-checking text fixtures are required for regression testing 
You can write an arbitrary program in Verilog 
Initial Blocks 
•? Like always blocks 
–? execute once at the very beginning of simulation 
–? not synthesizeable 
•? use reset instead 
Verilog Clock Generator 
module clockGenerator (CLK); 
  parameter period = 10; 
  parameter howlong = 100; 
  output  reg CLK; 
  initial begin 
    CLK = 0; 
    #(period/2); 
    repeat (howlong) begin 
      CLK = 1; 
      #(period-period/2); 
      CLK = 0; 
      #(period/2); 
    end 
    $finish; 
  end 
endmodule 
Finishes the simulation 
Cannot be restarted 
Page 5


Test Fixtures 
•? Provides clock 
•? Provides test vectors/checks results 
–? test vectors and results are precomputed 
–? usually read vectors from file 
•? Models system environment 
–? Complex program that simulates external environment 
•? Test fixture can all the language features 
–? initial, delays, read/write files, etc. 
Simulation 
Test Fixture 
(Specification) 
Circuit Description 
(Synthesizeable) 
Test Fixtures 
Verilog programs used to drive the simulation 
Much easier than drawing waveforms 
Test fixtures are usually non-synthesizeable 
Anything goes!   Really is like writing a C program 
Not really Verilog! 
Self-checking text fixtures are required for regression testing 
You can write an arbitrary program in Verilog 
Initial Blocks 
•? Like always blocks 
–? execute once at the very beginning of simulation 
–? not synthesizeable 
•? use reset instead 
Verilog Clock Generator 
module clockGenerator (CLK); 
  parameter period = 10; 
  parameter howlong = 100; 
  output  reg CLK; 
  initial begin 
    CLK = 0; 
    #(period/2); 
    repeat (howlong) begin 
      CLK = 1; 
      #(period-period/2); 
      CLK = 0; 
      #(period/2); 
    end 
    $finish; 
  end 
endmodule 
Finishes the simulation 
Cannot be restarted 
Another Clock Generator 
module clock_gen (masterclk); 
   `define PERIOD = 10; 
 output masterclk; 
 reg    masterclk; 
 initial masterclk = 0; 
 always begin 
  #`PERIOD/2 
  masterclk = ~masterclk; 
 end 
endmodule 
use `define to make constants  
easier to find and change 
use of initial and always 
blocks