Formula Sheets ALU, Data Path & Control Unit - Computer Architecture

 Page 1


ALU, Data P ath, and Con trol Unit F orm ula Sheet
Arithmetic and Logic Unit (ALU) Basics
• Definition : P erforms arithmetic (e.g., ADD, SUB) and logical (e.g., AND, OR, X OR) op erations.
• Op eration Time : T
ALU
, v aries b y op eration:
– A ddition/Subtraction: T
add
˜ 1 cycle.
– Multiplication: T
m ul
˜ 2-4 cycles.
– Division: T
div
˜ 10-20 cycles.
• Input/Output : Op erands (A,B , width w bits), Result (w bits), Status flags (e.g., Zero, Carry ,
Ov erflo w).
• ALU Width : w = 32 or 64 bits (e.g., 64-bit pro cessor), affec ts precision.
• A dder Dela y : T
adder
=O(logw) for carry-lo okahead, O(w) for ripple-carry .
• Op eration Selection : Con trolled b y k -bit op co de, N
ops
= 2
k
p ossible op erations.
Data P ath
• Definition : Hardw are comp onen ts (registers, ALU, m uxes, memory) and connections for instruc-
tion execution.
• Single-Cycle Data P ath :
– Executes one instruction p er clo c k cycle.
– Clo c k Cycle Time: T
cycle
=T
fetc h
+T
deco de
+T
ALU
+T
mem
+T
write-bac k
.
– Throughput: IPS =
f
1
, where f =
1
T
cycle
.
– Latency: T
instr
=T
cycle
.
• Pip elined Data P ath :
– Stages: F etc h, Deco de, Execute, Memory , W rite-Bac k (t ypically 5 stages).
– Pip eline Cycle Time: T
cycle
= max(T
stage
i
)+T
setup
, w here T
setup
is latc h o v erhead.
– Throughput: IPS˜f , ideally one instruction p er cycle.
– Latency: T
instr
=k·T
cycle
, w here k is n um b er of s tages.
– Pip eline Stalls: T
stall
=n
stall
·T
cycle
, e.g., data hazard (n
stall
= 1-2 ), branc h misprediction
(n
stall
= 2-3 ).
• Register File : N
regs
registers, eac h w bits, S
regfile
=N
regs
·w .
• Multiplexer Dela y : T
m ux
? logN
inputs
, t ypically negligible.
Con trol Unit
• Definition : Generates con trol signals for data path based on instruction op co de.
• T yp es :
– Hardwired: Fixed logic, T
con trol
˜T
deco de
, faster but less flexible.
– Microprogrammed: Con trol signals from microinstructions,T
con trol
=T
micro-fetc h
+T
micro-exec
.
• Con trol Signals : Enable/disable registers, select ALU op, memory read/write, PC up date.
• Con trol Unit Dela y : T
con trol
, affects T
cycle
in single-cycle, T
deco de
in pip eline.
• Microinstruction F ormat : Fields for ALU op, register con trol, memory con trol, next microin-
struction address.
1
Page 2


ALU, Data P ath, and Con trol Unit F orm ula Sheet
Arithmetic and Logic Unit (ALU) Basics
• Definition : P erforms arithmetic (e.g., ADD, SUB) and logical (e.g., AND, OR, X OR) op erations.
• Op eration Time : T
ALU
, v aries b y op eration:
– A ddition/Subtraction: T
add
˜ 1 cycle.
– Multiplication: T
m ul
˜ 2-4 cycles.
– Division: T
div
˜ 10-20 cycles.
• Input/Output : Op erands (A,B , width w bits), Result (w bits), Status flags (e.g., Zero, Carry ,
Ov erflo w).
• ALU Width : w = 32 or 64 bits (e.g., 64-bit pro cessor), affec ts precision.
• A dder Dela y : T
adder
=O(logw) for carry-lo okahead, O(w) for ripple-carry .
• Op eration Selection : Con trolled b y k -bit op co de, N
ops
= 2
k
p ossible op erations.
Data P ath
• Definition : Hardw are comp onen ts (registers, ALU, m uxes, memory) and connections for instruc-
tion execution.
• Single-Cycle Data P ath :
– Executes one instruction p er clo c k cycle.
– Clo c k Cycle Time: T
cycle
=T
fetc h
+T
deco de
+T
ALU
+T
mem
+T
write-bac k
.
– Throughput: IPS =
f
1
, where f =
1
T
cycle
.
– Latency: T
instr
=T
cycle
.
• Pip elined Data P ath :
– Stages: F etc h, Deco de, Execute, Memory , W rite-Bac k (t ypically 5 stages).
– Pip eline Cycle Time: T
cycle
= max(T
stage
i
)+T
setup
, w here T
setup
is latc h o v erhead.
– Throughput: IPS˜f , ideally one instruction p er cycle.
– Latency: T
instr
=k·T
cycle
, w here k is n um b er of s tages.
– Pip eline Stalls: T
stall
=n
stall
·T
cycle
, e.g., data hazard (n
stall
= 1-2 ), branc h misprediction
(n
stall
= 2-3 ).
• Register File : N
regs
registers, eac h w bits, S
regfile
=N
regs
·w .
• Multiplexer Dela y : T
m ux
? logN
inputs
, t ypically negligible.
Con trol Unit
• Definition : Generates con trol signals for data path based on instruction op co de.
• T yp es :
– Hardwired: Fixed logic, T
con trol
˜T
deco de
, faster but less flexible.
– Microprogrammed: Con trol signals from microinstructions,T
con trol
=T
micro-fetc h
+T
micro-exec
.
• Con trol Signals : Enable/disable registers, select ALU op, memory read/write, PC up date.
• Con trol Unit Dela y : T
con trol
, affects T
cycle
in single-cycle, T
deco de
in pip eline.
• Microinstruction F ormat : Fields for ALU op, register con trol, memory con trol, next microin-
struction address.
1
– Size: S
microinstr
=
?
S
field i
, e.g., 32-64 bits.
– Num b er of Microinstructions: N
micro
? N
instr
·C
complexit y
, where C
complexit y
is steps p er
instruction.
• Horizon tal Microprogramming : Wide microinstructions, S
microinstr
» , one signal p er bit,
T
exec
˜T
micro-fetc h
.
• V ertical Microprogramming : Narro w microinstructions, enco ded fields, T
exec
= T
micro-fetc h
+
T
deco de-field
.
RISC vs. CISC Impact
• RISC :
– Simple ALU ops, T
ALU
˜ 1 cycle.
– Single-cycle or pip elined data path, T
cycle
˜T
ALU
+T
reg
.
– Hardwired con trol, T
con trol
«T
microprogrammed
.
– Pip eline-friendly , CPI˜ 1 , stalls due to hazards.
• CISC :
– Complex ALU ops, T
ALU
= 1-20 cycles.
– Multi-cycle data path, T
instr
?C
complexit y
.
– Microprogrammed con trol, T
con trol
?N
microinstr
.
– Higher CPI, CPI = 2-10 , few er instructions N .
• Instruction Coun t : N
RISC
>N
CISC
, but T
exec-RISC
<T
exec-CISC
due to lo w er CPI and T
cycle
.
Microinstruction Execution
• Microprogram Execution Time : T
micro
=N
microinstr
·T
micro-cycle
, whereT
micro-cycle
=T
micro-fetc h
+
T
micro-exec
.
• Con trol Store Size : S
con trol
=N
microinstr
·S
microinstr
, t ypically 2
10
-2
12
microinstructions.
• Next A ddress Logic : Next
addr
=f( op co de, status flags , seq field ) , T
seq
˜T
m ux
.
• Sym b olic Microinstructions : Human-readable, compiled to binary , S
sym b olic
»S
binary
.
• Branc h Microinstructions : T
branc h
=T
micro-cycle
+T
addr-calc
, increases T
micro
.
P erformance Metrics
• Execution Time : T
exec
=N· CPI·T
cycle
, where N is instruction coun t, T
cycle
=
1
f
.
• Throughput : I PS =
f
CPI
, MIPS =
IPS
10
6
.
• Pip eline E?iciency : Throughput˜
f
1+ stalls/CPI
, stalls from data/con trol hazards.
• ALU Utilization : U
ALU
=
T
ALU-used
T
total
, higher in RISC.
• Con trol Unit Ov erhead : T
con trol
/T
cycle
, lo w er in h ardwired.
• Amdahl’s La w : Sp eedup S =
1
(1-P)+
P
k
, where P is parallelizable fraction, k is sp eedup (e.g.,
pip eline stages).
2
Page 3


ALU, Data P ath, and Con trol Unit F orm ula Sheet
Arithmetic and Logic Unit (ALU) Basics
• Definition : P erforms arithmetic (e.g., ADD, SUB) and logical (e.g., AND, OR, X OR) op erations.
• Op eration Time : T
ALU
, v aries b y op eration:
– A ddition/Subtraction: T
add
˜ 1 cycle.
– Multiplication: T
m ul
˜ 2-4 cycles.
– Division: T
div
˜ 10-20 cycles.
• Input/Output : Op erands (A,B , width w bits), Result (w bits), Status flags (e.g., Zero, Carry ,
Ov erflo w).
• ALU Width : w = 32 or 64 bits (e.g., 64-bit pro cessor), affec ts precision.
• A dder Dela y : T
adder
=O(logw) for carry-lo okahead, O(w) for ripple-carry .
• Op eration Selection : Con trolled b y k -bit op co de, N
ops
= 2
k
p ossible op erations.
Data P ath
• Definition : Hardw are comp onen ts (registers, ALU, m uxes, memory) and connections for instruc-
tion execution.
• Single-Cycle Data P ath :
– Executes one instruction p er clo c k cycle.
– Clo c k Cycle Time: T
cycle
=T
fetc h
+T
deco de
+T
ALU
+T
mem
+T
write-bac k
.
– Throughput: IPS =
f
1
, where f =
1
T
cycle
.
– Latency: T
instr
=T
cycle
.
• Pip elined Data P ath :
– Stages: F etc h, Deco de, Execute, Memory , W rite-Bac k (t ypically 5 stages).
– Pip eline Cycle Time: T
cycle
= max(T
stage
i
)+T
setup
, w here T
setup
is latc h o v erhead.
– Throughput: IPS˜f , ideally one instruction p er cycle.
– Latency: T
instr
=k·T
cycle
, w here k is n um b er of s tages.
– Pip eline Stalls: T
stall
=n
stall
·T
cycle
, e.g., data hazard (n
stall
= 1-2 ), branc h misprediction
(n
stall
= 2-3 ).
• Register File : N
regs
registers, eac h w bits, S
regfile
=N
regs
·w .
• Multiplexer Dela y : T
m ux
? logN
inputs
, t ypically negligible.
Con trol Unit
• Definition : Generates con trol signals for data path based on instruction op co de.
• T yp es :
– Hardwired: Fixed logic, T
con trol
˜T
deco de
, faster but less flexible.
– Microprogrammed: Con trol signals from microinstructions,T
con trol
=T
micro-fetc h
+T
micro-exec
.
• Con trol Signals : Enable/disable registers, select ALU op, memory read/write, PC up date.
• Con trol Unit Dela y : T
con trol
, affects T
cycle
in single-cycle, T
deco de
in pip eline.
• Microinstruction F ormat : Fields for ALU op, register con trol, memory con trol, next microin-
struction address.
1
– Size: S
microinstr
=
?
S
field i
, e.g., 32-64 bits.
– Num b er of Microinstructions: N
micro
? N
instr
·C
complexit y
, where C
complexit y
is steps p er
instruction.
• Horizon tal Microprogramming : Wide microinstructions, S
microinstr
» , one signal p er bit,
T
exec
˜T
micro-fetc h
.
• V ertical Microprogramming : Narro w microinstructions, enco ded fields, T
exec
= T
micro-fetc h
+
T
deco de-field
.
RISC vs. CISC Impact
• RISC :
– Simple ALU ops, T
ALU
˜ 1 cycle.
– Single-cycle or pip elined data path, T
cycle
˜T
ALU
+T
reg
.
– Hardwired con trol, T
con trol
«T
microprogrammed
.
– Pip eline-friendly , CPI˜ 1 , stalls due to hazards.
• CISC :
– Complex ALU ops, T
ALU
= 1-20 cycles.
– Multi-cycle data path, T
instr
?C
complexit y
.
– Microprogrammed con trol, T
con trol
?N
microinstr
.
– Higher CPI, CPI = 2-10 , few er instructions N .
• Instruction Coun t : N
RISC
>N
CISC
, but T
exec-RISC
<T
exec-CISC
due to lo w er CPI and T
cycle
.
Microinstruction Execution
• Microprogram Execution Time : T
micro
=N
microinstr
·T
micro-cycle
, whereT
micro-cycle
=T
micro-fetc h
+
T
micro-exec
.
• Con trol Store Size : S
con trol
=N
microinstr
·S
microinstr
, t ypically 2
10
-2
12
microinstructions.
• Next A ddress Logic : Next
addr
=f( op co de, status flags , seq field ) , T
seq
˜T
m ux
.
• Sym b olic Microinstructions : Human-readable, compiled to binary , S
sym b olic
»S
binary
.
• Branc h Microinstructions : T
branc h
=T
micro-cycle
+T
addr-calc
, increases T
micro
.
P erformance Metrics
• Execution Time : T
exec
=N· CPI·T
cycle
, where N is instruction coun t, T
cycle
=
1
f
.
• Throughput : I PS =
f
CPI
, MIPS =
IPS
10
6
.
• Pip eline E?iciency : Throughput˜
f
1+ stalls/CPI
, stalls from data/con trol hazards.
• ALU Utilization : U
ALU
=
T
ALU-used
T
total
, higher in RISC.
• Con trol Unit Ov erhead : T
con trol
/T
cycle
, lo w er in h ardwired.
• Amdahl’s La w : Sp eedup S =
1
(1-P)+
P
k
, where P is parallelizable fraction, k is sp eedup (e.g.,
pip eline stages).
2
Applications and Concepts
• ALU : Core of arithmetic/logical ops, used in all instructions, optimized for T
add
.
• Data P ath : Defines instruction flo w, single-cycle for simplicit y , pip elined for p erformance.
• Con trol Unit : Orc hestrates data path, microprogrammed for flexibilit y , hardwi red for sp eed.
• 64-Bit Pro cessor : Wider ALU/data path (w = 64 ), larger registers, S
regfile
= 64·N
regs
.
• A ddressing Mo des : Impact T
op erand
, in tegrated in to data path (e.g., indexed mo de uses ALU).
• P arallel Computing : Multi-ALU/data paths, T
exec
?
1
N cores
, limited b y Amdahl’s La w.
3