Formula sheet: Machine Instructions & Addressing Modes

 Page 1


Mac hine Ins tructions & A ddressing Mo des F orm ula
Sheet for GA TE (Digital Circuits)
Mac hine Instructions
• Definition : A mac hine instruction is a binary co de that a pro cessor executes to
p erform a sp ecific op eration.
• Instruction F ormat :
Instruction = Op co de+ Op erand(s)
where Op co de sp ecifies the op eration, and Op erand(s) sp ecify the data or memory
address.
• T yp es of Instructions :
– Data T ransfer: e.g., MO V, LO AD, STORE.
– Arithmetic: e.g., ADD, SUB, MUL, DIV.
– Logical: e.g., AND, OR, X OR, NOT.
– Con trol T ransfer: e.g., JMP , CALL, RET.
– Input/Output: e.g., IN, OUT.
• Instruction Cycle :
F etc h? Deco de? Execute? (Store)
• Instruction Length : Dep ends on arc hitecture (e.g., fixed-length in RISC, v ariable-
length in CISC).
• Program Coun ter (PC) : Holds the address of the next instruction to b e fetc hed.
PC? PC+ Instruction Length
• Instruction Execution Time :
T
total
=N·CPI·T
clo c k
where N is the n um b er of instructions, CPI is cycles p er instruction, T
clo c k
is clo c k
p erio d (s ).
A ddressing Mo des
• Definition : Sp ecifies ho w the op erand of an instruction is accessed (e.g., data lo cation
in memory or registers).
• Common A ddressing Mo des :
1
Page 2


Mac hine Ins tructions & A ddressing Mo des F orm ula
Sheet for GA TE (Digital Circuits)
Mac hine Instructions
• Definition : A mac hine instruction is a binary co de that a pro cessor executes to
p erform a sp ecific op eration.
• Instruction F ormat :
Instruction = Op co de+ Op erand(s)
where Op co de sp ecifies the op eration, and Op erand(s) sp ecify the data or memory
address.
• T yp es of Instructions :
– Data T ransfer: e.g., MO V, LO AD, STORE.
– Arithmetic: e.g., ADD, SUB, MUL, DIV.
– Logical: e.g., AND, OR, X OR, NOT.
– Con trol T ransfer: e.g., JMP , CALL, RET.
– Input/Output: e.g., IN, OUT.
• Instruction Cycle :
F etc h? Deco de? Execute? (Store)
• Instruction Length : Dep ends on arc hitecture (e.g., fixed-length in RISC, v ariable-
length in CISC).
• Program Coun ter (PC) : Holds the address of the next instruction to b e fetc hed.
PC? PC+ Instruction Length
• Instruction Execution Time :
T
total
=N·CPI·T
clo c k
where N is the n um b er of instructions, CPI is cycles p er instruction, T
clo c k
is clo c k
p erio d (s ).
A ddressing Mo des
• Definition : Sp ecifies ho w the op erand of an instruction is accessed (e.g., data lo cation
in memory or registers).
• Common A ddressing Mo des :
1
– Immediate : Op erand is part of the instruction.
Op erand = V alue
Example: ADD #5 (A dd 5 directly).
– Direct (Absolute) : Op erand is the memory address sp ecified in the instruction.
Effectiv e A ddress (EA) = A ddress Field
Example: LOAD 1000 (Load from memory address 1000).
– Indirect : Instruction sp ecifies the address of a memory lo cation that con tains
the op erand’s address.
EA = [ A ddress Field]
Example: LOAD (R1) (Load from address stored in register R1).
– Register : Op erand is in a register.
Op erand = Register Con ten t
Example: ADD R1, R2 (A dd con ten ts o f R1 and R2).
– Register Indirect : Register con tains the address of the op erand in memory .
EA = [ Register]
Example: LOAD [R1] (Load from memory address in R1).
– Indexed : Effectiv e address is the sum of a base address and an index.
EA = Base A ddress+ Index Register
Example: LOAD 100(R2) (Load from address 100 + con ten t of R2).
– Relativ e : Effectiv e address is relativ e to the program coun ter.
EA = PC+ Offset
Example: JMP +4 (Jump to PC + 4).
– Base Register : Uses a base register to calculate the effectiv e address.
EA = Base Register+ Offset
– Implied (Inheren t) : Op erand is implicitly defined b y the instruction.
Op erand = Implied b y Op co de
Example: CLR (Clear accum ulator).
• Stac k A ddressing : Op erands are accessed from the stac k (e.g., PUSH, POP).
EA = Stac k P oin ter (SP)
SP? SP±1 (after PUSH/POP)
2
Page 3


Mac hine Ins tructions & A ddressing Mo des F orm ula
Sheet for GA TE (Digital Circuits)
Mac hine Instructions
• Definition : A mac hine instruction is a binary co de that a pro cessor executes to
p erform a sp ecific op eration.
• Instruction F ormat :
Instruction = Op co de+ Op erand(s)
where Op co de sp ecifies the op eration, and Op erand(s) sp ecify the data or memory
address.
• T yp es of Instructions :
– Data T ransfer: e.g., MO V, LO AD, STORE.
– Arithmetic: e.g., ADD, SUB, MUL, DIV.
– Logical: e.g., AND, OR, X OR, NOT.
– Con trol T ransfer: e.g., JMP , CALL, RET.
– Input/Output: e.g., IN, OUT.
• Instruction Cycle :
F etc h? Deco de? Execute? (Store)
• Instruction Length : Dep ends on arc hitecture (e.g., fixed-length in RISC, v ariable-
length in CISC).
• Program Coun ter (PC) : Holds the address of the next instruction to b e fetc hed.
PC? PC+ Instruction Length
• Instruction Execution Time :
T
total
=N·CPI·T
clo c k
where N is the n um b er of instructions, CPI is cycles p er instruction, T
clo c k
is clo c k
p erio d (s ).
A ddressing Mo des
• Definition : Sp ecifies ho w the op erand of an instruction is accessed (e.g., data lo cation
in memory or registers).
• Common A ddressing Mo des :
1
– Immediate : Op erand is part of the instruction.
Op erand = V alue
Example: ADD #5 (A dd 5 directly).
– Direct (Absolute) : Op erand is the memory address sp ecified in the instruction.
Effectiv e A ddress (EA) = A ddress Field
Example: LOAD 1000 (Load from memory address 1000).
– Indirect : Instruction sp ecifies the address of a memory lo cation that con tains
the op erand’s address.
EA = [ A ddress Field]
Example: LOAD (R1) (Load from address stored in register R1).
– Register : Op erand is in a register.
Op erand = Register Con ten t
Example: ADD R1, R2 (A dd con ten ts o f R1 and R2).
– Register Indirect : Register con tains the address of the op erand in memory .
EA = [ Register]
Example: LOAD [R1] (Load from memory address in R1).
– Indexed : Effectiv e address is the sum of a base address and an index.
EA = Base A ddress+ Index Register
Example: LOAD 100(R2) (Load from address 100 + con ten t of R2).
– Relativ e : Effectiv e address is relativ e to the program coun ter.
EA = PC+ Offset
Example: JMP +4 (Jump to PC + 4).
– Base Register : Uses a base register to calculate the effectiv e address.
EA = Base Register+ Offset
– Implied (Inheren t) : Op erand is implicitly defined b y the instruction.
Op erand = Implied b y Op co de
Example: CLR (Clear accum ulator).
• Stac k A ddressing : Op erands are accessed from the stac k (e.g., PUSH, POP).
EA = Stac k P oin ter (SP)
SP? SP±1 (after PUSH/POP)
2
P e rformance Considerations
• Effectiv e A ddress Calculation Time : V aries b y addressing mo de (e.g., immediate
is fastest, indirect is slo w er).
• Memory A ccesses : Indirect and indexed mo des ma y require m ultiple memory ac-
cesses.
• Instruction Size : Immediate and direct mo des increase instruction length due to
address or data fields.
Key Notes
• F or GA TE, fo cus on iden tifying addressing mo des from instruction examples.
• Understand the impact of addressing mo des on instruction execution time.
• RISC arc hitectures prefer simpler addressing mo des (e.g., register, immediate).
• CISC arc hitectures supp ort complex mo des (e.g., indirect, indexed).
• Practice problems in v olving PC up dates and effectiv e address calculations.
3