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58 Videos | 314 Tests
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Topicwise Question Bank for Civil Engineering
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Topicwise Question Bank for Electronics Engineering
101 Tests
IIITH UGEE Mock Test Series
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Engineering Mathematics
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Digital Electronics
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General Knowledge
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217 Tests
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GATE SOLVED PAPER-ME GATE- 2003
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GATE Question Discussion
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Gate Numericals on Logic Gates
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PYQ GATE 2019
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PYQ GATE 2004
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PYQ GATE 2009
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PYQ GATE 2003
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PYQ GATE 2004
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GATE Questions
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GATE Questions
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GATE Question- 8
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GATE Question- 9
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GATE Question- 2
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GATE Question 18
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Practice Test: Gate Electrical Engineering GATE 2018 Paper
65 Questions | 180 min
Practice Test: Gate Electrical Engineering GATE 2015 Paper
65 Questions | 180 min
Practice Test: Gate Electrical Engineering GATE 2013 Paper
65 Questions | 180 min
Practice Test: Gate Electrical Engineering GATE 2017 Paper
65 Questions | 180 min
Practice Test: Gate Electrical Engineering GATE 2017 Paper
65 Questions | 180 min
Practice Test: Gate Electrical Engineering GATE 2014 Paper
65 Questions | 180 min
Practice Test: Gate Electrical Engineering GATE 2016 Paper
65 Questions | 180 min
GATE Chemistry Mock Test - 1
65 Questions | 180 min
GATE Chemistry Mock Test - 2
65 Questions | 180 min
GATE 2016 ME Set 1
25 Questions | 180 min
GATE Physics Mock Test Series - 6
60 Questions | 180 min
Gate Mock Test- 5: CS/IT
65 Questions | 180 min
Gate Mock Test- 11: CS/IT
65 Questions | 180 min
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Gate Mock Test- 15: CS/IT
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GATE Physics Mock Test Series - 8
60 Questions | 180 min
GATE Physics Mock Test Series - 7
60 Questions | 180 min
Gate Mock Test- 3: CS/IT
65 Questions | 180 min
GATE Physics Mock Test Series - 4
60 Questions | 180 min
Gate Mock Test Civil Engineering (CE)
65 Questions | 180 min
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65 Questions | 180 min
GATE Mock Test Mechanical Engineering (ME) - 10
65 Questions | 180 min
GATE Mock Test Electronics Engineering (ECE)- 15
65 Questions | 180 min
Past Year Paper - Mechanical Engineering GATE : 2019
65 Questions | 180 min
Chemistry- CY 2013 GATE Paper (Practice Test)
65 Questions | 180 min
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65 Questions | 180 min
Gate Mock Test: Electrical Engineering(EE)- 10
64 Questions | 180 min
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65 Questions | 180 min
Biotechnology - (BT) 2018 GATE Paper (Practice Test)
65 Questions | 180 min
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65 Questions | 180 min
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65 Questions | 180 min
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65 Questions | 180 min
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65 Questions | 180 min
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60 Questions | 180 min
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65 Questions | 180 min
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65 Questions | 180 min
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Bill Gates
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10 Videos
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21 Videos
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6 Videos
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Questions View All
Choose the correct options :a)The boolean expression of an AND gate followed by an inverter is same as the boolean expression for a NAND gate.b)The boolean expression for an OR gate followed by a NOT gate is same as that for a NOR gatec)No two basic logic gates have the same boolean expressiond)None of the aboveCorrect answer is option 'A,B,C'. Can you explain this answer?
3 answers
How many NAND gates are used to form an AND gate with explaination?
2 answers
Which among the following gates has output = A . B ?a)OR gateb)NOT gatec)AND gated)NAND gateCorrect answer is option 'C'. Can you explain this answer?
2 answers
The combination of gates shown below yieldsa)OR gateb)NOT gatec)AND gated)NAND gateCorrect answer is option 'A'. Can you explain this answer?
2 answers
Consider the following codeint DO(char *gate){char *gate1 = gate;char *gate2 = gate + strlen (gate) – 1;while (gate1 < =gate2){if (*gate1 ++! = *gate2 --)Return 0;}return 1;}Q. What is the functionality of above function Do ()?a)Check whether string is odd palindrome.b)Check whether the string is even palindromec)Check whether the string is palindromed)None of aboveCorrect answer is option 'C'. Can you explain this answer?
1 answers
Consider the following codeint DO(char *gate){char *gate1 = gate;char *gate2 = gate + strlen (gate) – 1;while (gate1 {if (*gate1 ++! = *gate2 --)Return 0;}return 1;}What is the functionality of the above function Do ()?a)Check whether string is an odd palindrome.b)Check whether the string is even palindromec)Check whether the string is palindromed)None of aboveCorrect answer is option 'C'. Can you explain this answer?
1 answers
Why NAND logic gate and NOR logic gate are called universal gates?
1 answers
2Not gates connected to nand gate as inputes then whole circuit represents what gate and why?
1 answers
The TRIAC’s terminals area)gate, anode, cathodeb)MT1, MT2, gatec)gate1, gate2, anode, cathoded)MT1, MT2, gate1, gate2Correct answer is option 'B'. Can you explain this answer?
1 answers
How many NOR gates are necessary to build NAND gate?
1 answers
A logic circuit with an outputconsists of :a)two AND gates and one OR gateb)two AND gates, one OR gate and one inverterc)two AND gates, one OR gate and two inverterd)two OR gates, one AND gate and two inverterCorrect answer is option 'C'. Can you explain this answer?
1 answers
The gates required to build a half adder area)EX-OR gate and NOR gateb)EX-OR gate and OR gatec)EX-OR gate and AND gated)Four NAND gatesCorrect answer is option 'C'. Can you explain this answer?
1 answers
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate.The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.Correct answer is '19.2'. Can you explain this answer?
1 answers
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate.The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.Correct answer is '12'. Can you explain this answer?
1 answers
The combination of NAND gates shown here (in figure), are equivalent toa)An OR gate and an AND gate respectivelyb)An AND gate and a NOT gate respectivelyc)An AND gate and an OR gate respectivelyd)An OR gate and a NOT gate respectivelyCorrect answer is option 'A'. Can you explain this answer?
1 answers
The gates required to build a half adder are:a)EX-OR gate and NOR gateb)Four NAND gatec)EX-OR gate and OR gated)EX-OR gate and AND gateCorrect answer is option 'D'. Can you explain this answer?
1 answers
A full adder circuit can be implemented using:1. One 3 x 8 decoder and two OR gates.2. One 3 x 8 decoder, one OR gate and a NOT gate.3. Two half adders and one OR gate.4. Two half adders and one NOT gate.5. Nine NAND/NOR gates.6. 6 NAND/NOR gates.Select the correct code from the given options.a)2, 4 and 5b)1, 4 and 6c)1, 3 and 5d)2, 3 and 6Correct answer is option 'C'. Can you explain this answer?
1 answers
Two NOT gates are connected at the two inputs of a NAND gate. This combination will behave likea)NAND gateb)AND gatec)OR gated)NOR gateCorrect answer is option 'A'. Can you explain this answer?
1 answers
Figure consists of two NOT gates followed by a NOR gate. This combination is equivalent to a singlea)NAND gateb)AND gatec)OR gated)XOR gateCorrect answer is option 'B'. Can you explain this answer?
1 answers
Which of the following gates cannot be prepared by the repetitive use of NOR gatea)AND gate b) OR gatec)NOT gated) None of theseCorrect answer is option 'D'. Can you explain this answer?
1 answers
The combination of gates shown below yieldsa)OR gateb)NOT gatec)XOR gate d)NAND gateCorrect answer is option 'A'. Can you explain this answer?
1 answers
The combination of gates shown below yieldsa)OR gateb)NOT gatec)XOR gated)NAND gateCorrect answer is option 'A'. Can you explain this answer?
1 answers
A and B are inputs for AND gate, C and D are inputs for NAND gate. Output of AND gate and NAND gate is fed to OR gate. What is the Output of OR gate?
1 answers
A 3-input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca . Which oneof the following gates is represented by the functiona)3-input NAND gateb)3-input XOR gatec)3-input NOR gated)3-input XNOR gateCorrect answer is option 'B,D'. Can you explain this answer?
1 answers
A pole has to be erected at a point on the boundary of a circular park of diameter 17 m in such a way that the difference of its distances from two diametrically opposite fixed gate A and B on the boundary is 7 m .Is it possible to do so ?If yes , at what distance from the two gates should the pole be erected?
1 answers
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Choose the correct options :a)The boolean expression of an AND gate followed by an inverter is same as the boolean expression for a NAND gate.b)The boolean expression for an OR gate followed by a NOT gate is same as that for a NOR gatec)No two basic logic gates have the same boolean expressiond)None of the aboveCorrect answer is option 'A,B,C'. Can you explain this answer?
3 answers
How many NAND gates are used to form an AND gate with explaination?
2 answers
Which among the following gates has output = A . B ?a)OR gateb)NOT gatec)AND gated)NAND gateCorrect answer is option 'C'. Can you explain this answer?
2 answers
The combination of gates shown below yieldsa)OR gateb)NOT gatec)AND gated)NAND gateCorrect answer is option 'A'. Can you explain this answer?
2 answers
Consider the following codeint DO(char *gate){char *gate1 = gate;char *gate2 = gate + strlen (gate) – 1;while (gate1 < =gate2){if (*gate1 ++! = *gate2 --)Return 0;}return 1;}Q. What is the functionality of above function Do ()?a)Check whether string is odd palindrome.b)Check whether the string is even palindromec)Check whether the string is palindromed)None of aboveCorrect answer is option 'C'. Can you explain this answer?
1 answers
Consider the following codeint DO(char *gate){char *gate1 = gate;char *gate2 = gate + strlen (gate) – 1;while (gate1 {if (*gate1 ++! = *gate2 --)Return 0;}return 1;}What is the functionality of the above function Do ()?a)Check whether string is an odd palindrome.b)Check whether the string is even palindromec)Check whether the string is palindromed)None of aboveCorrect answer is option 'C'. Can you explain this answer?
1 answers
Why NAND logic gate and NOR logic gate are called universal gates?
1 answers
2Not gates connected to nand gate as inputes then whole circuit represents what gate and why?
1 answers
The TRIAC’s terminals area)gate, anode, cathodeb)MT1, MT2, gatec)gate1, gate2, anode, cathoded)MT1, MT2, gate1, gate2Correct answer is option 'B'. Can you explain this answer?
1 answers
How many NOR gates are necessary to build NAND gate?
1 answers
A logic circuit with an outputconsists of :a)two AND gates and one OR gateb)two AND gates, one OR gate and one inverterc)two AND gates, one OR gate and two inverterd)two OR gates, one AND gate and two inverterCorrect answer is option 'C'. Can you explain this answer?
1 answers
The gates required to build a half adder area)EX-OR gate and NOR gateb)EX-OR gate and OR gatec)EX-OR gate and AND gated)Four NAND gatesCorrect answer is option 'C'. Can you explain this answer?
1 answers
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate.The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.Correct answer is '19.2'. Can you explain this answer?
1 answers
A half adder is implemented with XOR and AND gates. A full adder is implemented with two half adders and one OR gate.The propagation delay of an XOR gate is twice that of an AND/OR gate. The propagation delay of an AND/OR gate is 1.2 microseconds. A 4-bit-ripple-carry binary adder is implemented by using four full adders. The total propagation time of this 4-bit binary adder in microseconds is ______.Correct answer is '12'. Can you explain this answer?
1 answers
The combination of NAND gates shown here (in figure), are equivalent toa)An OR gate and an AND gate respectivelyb)An AND gate and a NOT gate respectivelyc)An AND gate and an OR gate respectivelyd)An OR gate and a NOT gate respectivelyCorrect answer is option 'A'. Can you explain this answer?
1 answers
The gates required to build a half adder are:a)EX-OR gate and NOR gateb)Four NAND gatec)EX-OR gate and OR gated)EX-OR gate and AND gateCorrect answer is option 'D'. Can you explain this answer?
1 answers
A full adder circuit can be implemented using:1. One 3 x 8 decoder and two OR gates.2. One 3 x 8 decoder, one OR gate and a NOT gate.3. Two half adders and one OR gate.4. Two half adders and one NOT gate.5. Nine NAND/NOR gates.6. 6 NAND/NOR gates.Select the correct code from the given options.a)2, 4 and 5b)1, 4 and 6c)1, 3 and 5d)2, 3 and 6Correct answer is option 'C'. Can you explain this answer?
1 answers
Two NOT gates are connected at the two inputs of a NAND gate. This combination will behave likea)NAND gateb)AND gatec)OR gated)NOR gateCorrect answer is option 'A'. Can you explain this answer?
1 answers
Figure consists of two NOT gates followed by a NOR gate. This combination is equivalent to a singlea)NAND gateb)AND gatec)OR gated)XOR gateCorrect answer is option 'B'. Can you explain this answer?
1 answers
Which of the following gates cannot be prepared by the repetitive use of NOR gatea)AND gate b) OR gatec)NOT gated) None of theseCorrect answer is option 'D'. Can you explain this answer?
1 answers
The combination of gates shown below yieldsa)OR gateb)NOT gatec)XOR gate d)NAND gateCorrect answer is option 'A'. Can you explain this answer?
1 answers
The combination of gates shown below yieldsa)OR gateb)NOT gatec)XOR gated)NAND gateCorrect answer is option 'A'. Can you explain this answer?
1 answers
A and B are inputs for AND gate, C and D are inputs for NAND gate. Output of AND gate and NAND gate is fed to OR gate. What is the Output of OR gate?
1 answers
A 3-input majority gate is defined by the logic function M(a,b,c) = ab + bc + ca . Which oneof the following gates is represented by the functiona)3-input NAND gateb)3-input XOR gatec)3-input NOR gated)3-input XNOR gateCorrect answer is option 'B,D'. Can you explain this answer?
1 answers
A pole has to be erected at a point on the boundary of a circular park of diameter 17 m in such a way that the difference of its distances from two diametrically opposite fixed gate A and B on the boundary is 7 m .Is it possible to do so ?If yes , at what distance from the two gates should the pole be erected?
1 answers