A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev

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Electrical Engineering (EE) : A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev

The document A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Digital Electronics.
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A 4-bit Reversible shift register.
 

The shift register in Fig 5.7.5 could be operated as:

  • A parallel in/parallel out register. (PIPO)
  • A Serial in/serial out register. (SISO)
  • A serial in/parallel out register. (SIPO)
  • A parallel in/serial out register. (PISO)

However Fig 5.7.5 can only shift data in one direction, i.e. left to right. To be truly versatile it could be an advantage to be able to shift data in both directions and in any of the four shift register operating modes. Fig. 5.7.6 achieves this by adding data steering circuitry.

 

The gating arrangement at the bottom of Fig 5.7.6 (gates G1 to G13) is exactly the same as that described above in Fig. 5.7.5, and these gates control the loading of parallel data.

Gates G14 to G28 in Fig 5.7.6 control the direction of data flow through the register. The JK flip-flops use the inverter gates G29 to G32 to ensure that J and K are at opposite logic states, so the flip-flops are  mimiking D Type operation, with J being used as the data input. Notice also that the clock is connected in the familiar synchronous mode.

 

A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev

 

 

Operation.

In any of the modes involving serial operation, data may be shifted left or shifted right by the application of a suitable logic level at the shift control A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev input.

With a logic 1 at this input the register is in the shift right mode, and data is taken into the ‘Serial in R’ input to be shifted right by application of successive clock pulses, appearing as parallel data, changing with each clock pulse, on the flip flop Q outputs. After four clock pulses the data begins to appear in serial form on the Q3output, which is also the ‘Serial Out R’ output.

The logic 1 on the shift control A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev enables gates G18, 20, 22 & 24, but because the logic 1 is inverted by G27, gates G19, 21, 23 & 25 are disabled.

The path of serial data (e.g. a logic 1) from left to right is as follows; the logic 1 appearing at the input to G26 is inverted and passes through G18 which re-inverts it to logic 1 and, as G19 is disabled its output must also be at logic 1. Both inputs to the AND gate G14 are at logic 1 and therefore so is its output, (AND gate rules) making the J input of FF0 logic 1.

On the arrival of a clock pulse, the logic 1 input to FF0 will appear on the output Q0. Its inverse (logic 0) will also appear on the A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev output of FF0. This logic 0 forms the input to the next multiplexer arrangement, gates G20, 21 & 15. As G20 is enabled (and G21 disabled) the logic 0 becomes logic 1 at G15 output and so is fed to the J input of FF1. This method is used to transfer data to each flip-flop in the chain.

To achieve shift left operation, the shift control A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev is set to logic 0 and so enables gates G19, 21, 23 & 25 while disabling gates G18, 20, 22 & 24. Therefore the A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev  output of FF3 is connected via G23 and G16 to the D input of FF2, the A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev output of FF2 is connected to the J input of FF1 via G21 and G15 (remember that G24 is disabled, so FF3 is isolated from this path). Finally, the A 4-bit Reversible Shift Register Electrical Engineering (EE) Notes | EduRev output of FF1 is connected via G19 and G14 to the J input of FF0, the Q0 output of which is also the ‘Serial Out L’ output. The ability to shift data in either direction, together with the parallel input and output facilities make this register a very versatile device.

It is common to connect shift register ICs in cascade, using the serial output of one register to connect to the serial input of the next register in the chain. For this reason both the data and clock inputs and outputs of register ICs are normally buffered.

Some examples from the many commercially available IC registers using these and similar methods, available in both CMOS and TTL versions, are listed below.

  • 74HC164 8-Bit SIPO Shift register from NXP
  • 74HC594 8-Bit SIPO/SISO with PIPO output storage register and dual clocks - from NXP
  • 74HC595 8-Bit SIPO/SISO with tri-state output PIPO storage register and dual clocks - from NXP
  • HEF4014B PISO Register with 8-bit synchronous parallel LOAD and outputs from Q5, Q6 & Q7 only - from NXP
  • CD4031B 64 Stage SISO shift register with re-circulation mode - from  Texas instruments.
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