Built in Self Test (Design Verification and Test of Digital VLSI Circuits) Notes | EduRev

: Built in Self Test (Design Verification and Test of Digital VLSI Circuits) Notes | EduRev

 Page 1


Design Verification and Test of 
Digital VLSI Circuits 
NPTEL Video Course 
Module-XI 
Lecture-I 
Built in Self Test 
Page 2


Design Verification and Test of 
Digital VLSI Circuits 
NPTEL Video Course 
Module-XI 
Lecture-I 
Built in Self Test 
Introduction 
•VLSI testing, only from the context where the circuit needs to be 
put to a “test mode” for validating that it is free of faults.  
•Circuits tested OK are shipped to the customers with the 
assumption that they would not fail within their expected life 
time; this is called off-line testing 
•However, this assumption does not hold for modern day ICs, 
based on deep sub-micron technology, because they may 
develop failures even during operation within expected life 
time. 
•To cater to this problem sometimes redundant circuitry are kept 
on-chip which replace the faulty parts.  
•Testing a circuit every time before they startup, is called Built-In-
Self-Test (BIST).  
Page 3


Design Verification and Test of 
Digital VLSI Circuits 
NPTEL Video Course 
Module-XI 
Lecture-I 
Built in Self Test 
Introduction 
•VLSI testing, only from the context where the circuit needs to be 
put to a “test mode” for validating that it is free of faults.  
•Circuits tested OK are shipped to the customers with the 
assumption that they would not fail within their expected life 
time; this is called off-line testing 
•However, this assumption does not hold for modern day ICs, 
based on deep sub-micron technology, because they may 
develop failures even during operation within expected life 
time. 
•To cater to this problem sometimes redundant circuitry are kept 
on-chip which replace the faulty parts.  
•Testing a circuit every time before they startup, is called Built-In-
Self-Test (BIST).  
Basic architecture of BIST 
CUT
with
DFT
Input
MUX
Normal
Input
Hardware Test Patten
Generator
Outputs
Output Response
Compactor
Primary
Outputs
Comparator
Signature
Status
ROM
Golden
Signature
Test Controller
Start BIST
Page 4


Design Verification and Test of 
Digital VLSI Circuits 
NPTEL Video Course 
Module-XI 
Lecture-I 
Built in Self Test 
Introduction 
•VLSI testing, only from the context where the circuit needs to be 
put to a “test mode” for validating that it is free of faults.  
•Circuits tested OK are shipped to the customers with the 
assumption that they would not fail within their expected life 
time; this is called off-line testing 
•However, this assumption does not hold for modern day ICs, 
based on deep sub-micron technology, because they may 
develop failures even during operation within expected life 
time. 
•To cater to this problem sometimes redundant circuitry are kept 
on-chip which replace the faulty parts.  
•Testing a circuit every time before they startup, is called Built-In-
Self-Test (BIST).  
Basic architecture of BIST 
CUT
with
DFT
Input
MUX
Normal
Input
Hardware Test Patten
Generator
Outputs
Output Response
Compactor
Primary
Outputs
Comparator
Signature
Status
ROM
Golden
Signature
Test Controller
Start BIST
Basic architecture of BIST 
Hardware Test Pattern Generator:  
•This module generates the test patterns required to sensitize the faults and 
propagate the effect to the outputs  
• As the test pattern generator is a circuit (not equipment) its area is limited.   
•So storing and then generating test patterns obtained by ATPG algorithms 
on the CUT (discussed in Module XI) using the hardware test pattern 
generator is not feasible.  
•Instead, the test pattern generator is basically a type of register which 
generates random patterns which act as test patterns. The main emphasis of 
the register design is to have low area yet generate as many different 
patterns (from 0 to 2
n
-1, if there are  n flip-flops in the register) as possible.   
 
Page 5


Design Verification and Test of 
Digital VLSI Circuits 
NPTEL Video Course 
Module-XI 
Lecture-I 
Built in Self Test 
Introduction 
•VLSI testing, only from the context where the circuit needs to be 
put to a “test mode” for validating that it is free of faults.  
•Circuits tested OK are shipped to the customers with the 
assumption that they would not fail within their expected life 
time; this is called off-line testing 
•However, this assumption does not hold for modern day ICs, 
based on deep sub-micron technology, because they may 
develop failures even during operation within expected life 
time. 
•To cater to this problem sometimes redundant circuitry are kept 
on-chip which replace the faulty parts.  
•Testing a circuit every time before they startup, is called Built-In-
Self-Test (BIST).  
Basic architecture of BIST 
CUT
with
DFT
Input
MUX
Normal
Input
Hardware Test Patten
Generator
Outputs
Output Response
Compactor
Primary
Outputs
Comparator
Signature
Status
ROM
Golden
Signature
Test Controller
Start BIST
Basic architecture of BIST 
Hardware Test Pattern Generator:  
•This module generates the test patterns required to sensitize the faults and 
propagate the effect to the outputs  
• As the test pattern generator is a circuit (not equipment) its area is limited.   
•So storing and then generating test patterns obtained by ATPG algorithms 
on the CUT (discussed in Module XI) using the hardware test pattern 
generator is not feasible.  
•Instead, the test pattern generator is basically a type of register which 
generates random patterns which act as test patterns. The main emphasis of 
the register design is to have low area yet generate as many different 
patterns (from 0 to 2
n
-1, if there are  n flip-flops in the register) as possible.   
 
Basic architecture of BIST 
Input Mux: This multiplexer is to allow normal inputs to the circuit when it is 
operational and test inputs from the pattern generator when BIST is executed. 
The control input of the multiplexer is fed by a central test controller.  
 
Output response compactor: Output response compacter performs lossy 
compression of the outputs of the CUT. The output of the CUT is to be compared 
with the expected response (called golden signature 
Similar to the situation for test pattern generator, expected output responses 
cannot be stored explicitly in a memory and compared with the responses of the 
CUT. So CUT response needs to be compacted such that comparisons with 
expected responses (golden signatures) become simpler in terms of area of the 
memory that stores the golden signatures. 
 
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