Case Study VLSI ? ? ?? ??? ?? Case Study VLSI ? ? ?? ??? ?? ) ( ) ( Notes | EduRev

: Case Study VLSI ? ? ?? ??? ?? Case Study VLSI ? ? ?? ??? ?? ) ( ) ( Notes | EduRev

 Page 1


Case Study 
VLSI ? ? ?? ??? ?? 
Page 2


Case Study 
VLSI ? ? ?? ??? ?? 
) ( ) (
0
m n x h n y
M
m
m
- =
?
=
) 1 ( ) 2 ( ) 3 ( ) 4 ( ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( ) 0 (
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
+ + + =
+ + + =
- + + + =
- + - + + =
- + - + - + =
) ( ) ( ) (
0 1
m n x h m n y k n y
M
m
m
M
m
m
- = - -
? ?
= =
) 1 ( ) 2 ( ) 3 ( ) 4 ( )] 1 ( ) 2 ( ) 3 ( [ ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( )] 0 ( ) 1 ( ) 2 ( [ ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( )] 1 ( ) 0 ( ) 1 ( [ ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( )] 2 ( ) 1 ( ) 0 ( [ ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( )] 3 ( ) 2 ( ) 1 ( [ ) 0 (
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
+ + = + + -
+ + = + + -
- + + = - + + -
- - + + = - + - + -
- - + - + = - + - + - -
   
1 -
z
1 -
z
1 -
z
0
h
1
h
2
h
M
h
+ + + 
? ? ? 
? ? ? 
) (n x
) (n x ) 1 ( - n x ) 2 ( - n x
) ( M n x -
   
1 -
z M
h
+ 
: delay : multiplier : adder 
) (n y
   
1 -
z
   
1 -
z
   
1 -
z
… 
+ 
+ 
+ 
n
h
0
h
1
h
2
h
+ 
+ 
… 
+ 
… 
n
k
1
k
2
k
   
1 -
z
   
1 -
z
   
1 -
z
… 
) (n x
) 1 ( - n x
) 2 ( - n x
) ( M n x -
) (n y
) 1 ( - n y
) 2 ( - n y
) ( M n y -
) (n v
FIR 
Filter tap=4 
IIR 
Case - Filter (1/8) 
Page 3


Case Study 
VLSI ? ? ?? ??? ?? 
) ( ) (
0
m n x h n y
M
m
m
- =
?
=
) 1 ( ) 2 ( ) 3 ( ) 4 ( ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( ) 0 (
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
+ + + =
+ + + =
- + + + =
- + - + + =
- + - + - + =
) ( ) ( ) (
0 1
m n x h m n y k n y
M
m
m
M
m
m
- = - -
? ?
= =
) 1 ( ) 2 ( ) 3 ( ) 4 ( )] 1 ( ) 2 ( ) 3 ( [ ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( )] 0 ( ) 1 ( ) 2 ( [ ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( )] 1 ( ) 0 ( ) 1 ( [ ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( )] 2 ( ) 1 ( ) 0 ( [ ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( )] 3 ( ) 2 ( ) 1 ( [ ) 0 (
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
+ + = + + -
+ + = + + -
- + + = - + + -
- - + + = - + - + -
- - + - + = - + - + - -
   
1 -
z
1 -
z
1 -
z
0
h
1
h
2
h
M
h
+ + + 
? ? ? 
? ? ? 
) (n x
) (n x ) 1 ( - n x ) 2 ( - n x
) ( M n x -
   
1 -
z M
h
+ 
: delay : multiplier : adder 
) (n y
   
1 -
z
   
1 -
z
   
1 -
z
… 
+ 
+ 
+ 
n
h
0
h
1
h
2
h
+ 
+ 
… 
+ 
… 
n
k
1
k
2
k
   
1 -
z
   
1 -
z
   
1 -
z
… 
) (n x
) 1 ( - n x
) 2 ( - n x
) ( M n x -
) (n y
) 1 ( - n y
) 2 ( - n y
) ( M n y -
) (n v
FIR 
Filter tap=4 
IIR 
Case - Filter (1/8) 
module fir1(a, b, c, y); 
input [7:0] a, b, c; 
output [11:0] y; 
assign y = a*2+b*4+c*6; 
endmodule 
 
module fir2(a, b, c, y); 
input [7:0] a, b, c; 
output [11:0] y; 
reg [11:0] y; 
always @(a or b or c) 
y = a*2+b*4+c*6; 
endmodule 
 
tap=3 
h
0
=2; h
1
=4, h
2
=6; 
Case - Filter (2/8) 
X 
X 
X 
+ 
+ 
2 
a 
4 
b 
6 
c 
y 
Output: 20, 32, 44, 56, 68, 80, 92, 104, …. 
delay delay 
Page 4


Case Study 
VLSI ? ? ?? ??? ?? 
) ( ) (
0
m n x h n y
M
m
m
- =
?
=
) 1 ( ) 2 ( ) 3 ( ) 4 ( ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( ) 0 (
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
+ + + =
+ + + =
- + + + =
- + - + + =
- + - + - + =
) ( ) ( ) (
0 1
m n x h m n y k n y
M
m
m
M
m
m
- = - -
? ?
= =
) 1 ( ) 2 ( ) 3 ( ) 4 ( )] 1 ( ) 2 ( ) 3 ( [ ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( )] 0 ( ) 1 ( ) 2 ( [ ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( )] 1 ( ) 0 ( ) 1 ( [ ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( )] 2 ( ) 1 ( ) 0 ( [ ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( )] 3 ( ) 2 ( ) 1 ( [ ) 0 (
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
+ + = + + -
+ + = + + -
- + + = - + + -
- - + + = - + - + -
- - + - + = - + - + - -
   
1 -
z
1 -
z
1 -
z
0
h
1
h
2
h
M
h
+ + + 
? ? ? 
? ? ? 
) (n x
) (n x ) 1 ( - n x ) 2 ( - n x
) ( M n x -
   
1 -
z M
h
+ 
: delay : multiplier : adder 
) (n y
   
1 -
z
   
1 -
z
   
1 -
z
… 
+ 
+ 
+ 
n
h
0
h
1
h
2
h
+ 
+ 
… 
+ 
… 
n
k
1
k
2
k
   
1 -
z
   
1 -
z
   
1 -
z
… 
) (n x
) 1 ( - n x
) 2 ( - n x
) ( M n x -
) (n y
) 1 ( - n y
) 2 ( - n y
) ( M n y -
) (n v
FIR 
Filter tap=4 
IIR 
Case - Filter (1/8) 
module fir1(a, b, c, y); 
input [7:0] a, b, c; 
output [11:0] y; 
assign y = a*2+b*4+c*6; 
endmodule 
 
module fir2(a, b, c, y); 
input [7:0] a, b, c; 
output [11:0] y; 
reg [11:0] y; 
always @(a or b or c) 
y = a*2+b*4+c*6; 
endmodule 
 
tap=3 
h
0
=2; h
1
=4, h
2
=6; 
Case - Filter (2/8) 
X 
X 
X 
+ 
+ 
2 
a 
4 
b 
6 
c 
y 
Output: 20, 32, 44, 56, 68, 80, 92, 104, …. 
delay delay 
module fir3(a, b, c, y, ck); 
input [7:0] a, b, c; 
input ck; 
output [11:0] y; 
reg [11:0] y; 
always @(posedge ck) 
y = a*2+b*4+c*6; 
endmodule 
 
X 
X 
X 
+ 
+ 
2 
a 
4 
b 
6 
c 
y 
reg 
ck 
Case - Filter (3/8) 
Three inputs (a, b, c) must be entered concurrently (more pins, higher cost). 
delay 
delay 
Output: 20, 32, 44, 56, 68, 80, 92, 104, …. 
Stable output 
The stable output is generated at the positive edge of clock. 
Page 5


Case Study 
VLSI ? ? ?? ??? ?? 
) ( ) (
0
m n x h n y
M
m
m
- =
?
=
) 1 ( ) 2 ( ) 3 ( ) 4 ( ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( ) 0 (
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
3 2 1 0
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
x h x h x h x h y
+ + + =
+ + + =
- + + + =
- + - + + =
- + - + - + =
) ( ) ( ) (
0 1
m n x h m n y k n y
M
m
m
M
m
m
- = - -
? ?
= =
) 1 ( ) 2 ( ) 3 ( ) 4 ( )] 1 ( ) 2 ( ) 3 ( [ ) 4 (
) 0 ( ) 1 ( ) 2 ( ) 3 ( )] 0 ( ) 1 ( ) 2 ( [ ) 3 (
) 1 ( ) 0 ( ) 1 ( ) 2 ( )] 1 ( ) 0 ( ) 1 ( [ ) 2 (
) 2 ( ) 1 ( ) 0 ( ) 1 ( )] 2 ( ) 1 ( ) 0 ( [ ) 1 (
) 3 ( ) 2 ( ) 1 ( ) 0 ( )] 3 ( ) 2 ( ) 1 ( [ ) 0 (
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
3 2 1 0 3 2 1
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
x h x h x h x h y k y k y k y
+ + = + + -
+ + = + + -
- + + = - + + -
- - + + = - + - + -
- - + - + = - + - + - -
   
1 -
z
1 -
z
1 -
z
0
h
1
h
2
h
M
h
+ + + 
? ? ? 
? ? ? 
) (n x
) (n x ) 1 ( - n x ) 2 ( - n x
) ( M n x -
   
1 -
z M
h
+ 
: delay : multiplier : adder 
) (n y
   
1 -
z
   
1 -
z
   
1 -
z
… 
+ 
+ 
+ 
n
h
0
h
1
h
2
h
+ 
+ 
… 
+ 
… 
n
k
1
k
2
k
   
1 -
z
   
1 -
z
   
1 -
z
… 
) (n x
) 1 ( - n x
) 2 ( - n x
) ( M n x -
) (n y
) 1 ( - n y
) 2 ( - n y
) ( M n y -
) (n v
FIR 
Filter tap=4 
IIR 
Case - Filter (1/8) 
module fir1(a, b, c, y); 
input [7:0] a, b, c; 
output [11:0] y; 
assign y = a*2+b*4+c*6; 
endmodule 
 
module fir2(a, b, c, y); 
input [7:0] a, b, c; 
output [11:0] y; 
reg [11:0] y; 
always @(a or b or c) 
y = a*2+b*4+c*6; 
endmodule 
 
tap=3 
h
0
=2; h
1
=4, h
2
=6; 
Case - Filter (2/8) 
X 
X 
X 
+ 
+ 
2 
a 
4 
b 
6 
c 
y 
Output: 20, 32, 44, 56, 68, 80, 92, 104, …. 
delay delay 
module fir3(a, b, c, y, ck); 
input [7:0] a, b, c; 
input ck; 
output [11:0] y; 
reg [11:0] y; 
always @(posedge ck) 
y = a*2+b*4+c*6; 
endmodule 
 
X 
X 
X 
+ 
+ 
2 
a 
4 
b 
6 
c 
y 
reg 
ck 
Case - Filter (3/8) 
Three inputs (a, b, c) must be entered concurrently (more pins, higher cost). 
delay 
delay 
Output: 20, 32, 44, 56, 68, 80, 92, 104, …. 
Stable output 
The stable output is generated at the positive edge of clock. 
fir2 
Case - Filter (4/8) 
fir2 
fir3 
Unstable output 
Stable output 
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