Codesign Extended Applications Computer Science Engineering (CSE) Notes | EduRev

Computer Science Engineering (CSE) : Codesign Extended Applications Computer Science Engineering (CSE) Notes | EduRev

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1 
Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid* 
Dept of Computer Science & Engineering 
University of California, Riverside 
*Also with the Center for Embedded Computer Systems at UC Irvine 
 
This work was supported in part by the National Science Foundation 
and by NEC C&C Research Labs 
Page 2


1 
Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid* 
Dept of Computer Science & Engineering 
University of California, Riverside 
*Also with the Center for Embedded Computer Systems at UC Irvine 
 
This work was supported in part by the National Science Foundation 
and by NEC C&C Research Labs 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-2 
Outline 
? Introduction: Hardware/Software Partitioning 
? And the common assumption of a single specification 
? Different Algorithms in Hardware/Software 
? Codesign Extended Applications 
? Experiments 
? Future Work and Conclusions 
Page 3


1 
Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid* 
Dept of Computer Science & Engineering 
University of California, Riverside 
*Also with the Center for Embedded Computer Systems at UC Irvine 
 
This work was supported in part by the National Science Foundation 
and by NEC C&C Research Labs 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-2 
Outline 
? Introduction: Hardware/Software Partitioning 
? And the common assumption of a single specification 
? Different Algorithms in Hardware/Software 
? Codesign Extended Applications 
? Experiments 
? Future Work and Conclusions 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-3 
Introduction – Hw/Sw Partitioning 
? Hw/sw partitioning can speedup software 
? Shown by numerous researchers 
? E.g., Balboni, Fornaciari, Sciuto CODES’96; Eles, Peng, Kuchchinski, Doboli 
DAES’97; Gajski, Vahid, Narayan, Gong Prentice-Hall 1997; Grode, Knudsen, 
Madsen DATE’98; many others 
? 1.5 to 10x common 
? Some examples like image processing get 100-800x speedup  
? E.g., Cameron project, FCCM’02 
? Can reduce energy too 
? E.g. 
? Henkel, Li CODES’98 
? Wan, Ichikawa, Lidsky, Rabaey CICC’98 
? Stitt, Grattan, Villarreal, Vahid FCCM’02 
? 60-80% energy savings measured on real single-chip uP/FPGA devices 
 
 
 
Page 4


1 
Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid* 
Dept of Computer Science & Engineering 
University of California, Riverside 
*Also with the Center for Embedded Computer Systems at UC Irvine 
 
This work was supported in part by the National Science Foundation 
and by NEC C&C Research Labs 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-2 
Outline 
? Introduction: Hardware/Software Partitioning 
? And the common assumption of a single specification 
? Different Algorithms in Hardware/Software 
? Codesign Extended Applications 
? Experiments 
? Future Work and Conclusions 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-3 
Introduction – Hw/Sw Partitioning 
? Hw/sw partitioning can speedup software 
? Shown by numerous researchers 
? E.g., Balboni, Fornaciari, Sciuto CODES’96; Eles, Peng, Kuchchinski, Doboli 
DAES’97; Gajski, Vahid, Narayan, Gong Prentice-Hall 1997; Grode, Knudsen, 
Madsen DATE’98; many others 
? 1.5 to 10x common 
? Some examples like image processing get 100-800x speedup  
? E.g., Cameron project, FCCM’02 
? Can reduce energy too 
? E.g. 
? Henkel, Li CODES’98 
? Wan, Ichikawa, Lidsky, Rabaey CICC’98 
? Stitt, Grattan, Villarreal, Vahid FCCM’02 
? 60-80% energy savings measured on real single-chip uP/FPGA devices 
 
 
 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-4 
Hw/Sw Partitioning on Single-Chip 
Platforms 
? Numerous single-chip 
commercial devices with uP 
and FPGA 
? Triscend E5 (shown) 
? Triscend A7 
? Atmel FPSLIC 
? Xilinx Virtex II Pro 
? Altera Excalibur 
? More sure to come… 
? Make hw/sw partitioning 
even more attractive 
uP and peripherals Cache/memory 
Configurable logic 
Page 5


1 
Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid* 
Dept of Computer Science & Engineering 
University of California, Riverside 
*Also with the Center for Embedded Computer Systems at UC Irvine 
 
This work was supported in part by the National Science Foundation 
and by NEC C&C Research Labs 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-2 
Outline 
? Introduction: Hardware/Software Partitioning 
? And the common assumption of a single specification 
? Different Algorithms in Hardware/Software 
? Codesign Extended Applications 
? Experiments 
? Future Work and Conclusions 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-3 
Introduction – Hw/Sw Partitioning 
? Hw/sw partitioning can speedup software 
? Shown by numerous researchers 
? E.g., Balboni, Fornaciari, Sciuto CODES’96; Eles, Peng, Kuchchinski, Doboli 
DAES’97; Gajski, Vahid, Narayan, Gong Prentice-Hall 1997; Grode, Knudsen, 
Madsen DATE’98; many others 
? 1.5 to 10x common 
? Some examples like image processing get 100-800x speedup  
? E.g., Cameron project, FCCM’02 
? Can reduce energy too 
? E.g. 
? Henkel, Li CODES’98 
? Wan, Ichikawa, Lidsky, Rabaey CICC’98 
? Stitt, Grattan, Villarreal, Vahid FCCM’02 
? 60-80% energy savings measured on real single-chip uP/FPGA devices 
 
 
 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-4 
Hw/Sw Partitioning on Single-Chip 
Platforms 
? Numerous single-chip 
commercial devices with uP 
and FPGA 
? Triscend E5 (shown) 
? Triscend A7 
? Atmel FPSLIC 
? Xilinx Virtex II Pro 
? Altera Excalibur 
? More sure to come… 
? Make hw/sw partitioning 
even more attractive 
uP and peripherals Cache/memory 
Configurable logic 
CODES’02 – Codesign Extended Applications 
Brian Grattan, Greg Stitt, Frank Vahid, Univ. of California, Riverside 1-5 
Hw/Sw Partitioning – Commercial Tools 
Evolving 
? Commercial products 
evolving 
? Synopsys’ Nimble compiler 
(2000) attempt 
? Proceler  
? Microprocessor Report’s 2001 
Technology of the Year Award 
? Others coming… 
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