The major drawback of the SR flip-flop (i.e. its indeterminate output and non-allowed logic states) described in Digital Electronics Module 5.2 is overcome by the D type flip-flop. This flip-flop, shown in Fig. 5.3.1 together with its truth table and a typical schematic circuit symbol, may be called a Data flip-flop because of its ability to ‘latch’ and remember data, or a Delay flip-flop because latching and remembering data can be used to create a delay in the progress of that data through a circuit. To avoid the ambiguity in the title therefore, it is usually known simply as the D Type. The simplest form of D Type flip-flop is basically a high activated SR type with an additional inverter to ensure that the S and R inputs cannot both be high or both low at the same time. This simple modification prevents both the indeterminate and non-allowed states of the SR flip-flop. The S and R inputs are now replaced by a single D input, and all D type flip-flops have a clock input.
As long as the clock input is low, changes at the D input make no difference to the outputs. The truth table in Fig. 5.3.1 shows this as a ‘don’t care’ state (X). The basic D Type flip-flop shown in Fig. 5.3.1 is called a level triggered D Type flip-flop because whether the D input is active or not depends on the logic level of the clock input.
Provided that the CK input is high (at logic 1), then whichever logic state is at D will appear at output Q and (unlike the SR flip-flops) is always the inverse of Q).
In Fig. 5.3.1, if D = 1, then S must be 1 and R must be 0, therefore Q is SET to 1.
If D = 0 then R must be 1 and S must be 0, causing Q to be reset to 0.
The name Data Latch refers to a D Type flip-flop that is level triggered, as the data (1 or 0) appearing at D can be held or ‘latched’ at any time whilst the CK input is at a high level (logic 1).
As can be seen from the timing diagram shown in Fig 5.3.2, if the data at D changes during this time, the Q output assumes the same logic level as the D.
Fig. 5.3.2 also illustrates a possible problem with the level triggered D type flip-flop; if there are changes in the data during period when the clock pulse is at its high level, the logic state at Q changes in sympathy with D, and only ‘remembers’ the last input state that occurred during the clock pulse, (period RT in Fig. 5.3.2). This effect is called ‘Ripple Through’, and although this allows the level triggered D Type flip-flop to be used as a data switch, only allowing data through from D to Q as long as CK is held at logic 1, this may not be a desirable property in many types of circuit.
Fortunately ripple though can be largely prevented by using the Edge Triggered D Type flip-flop illustrated in Fig 5.3.3.
The clock pulse applied to the flip-flop is reduced to a very narrow positive going clock pulse of only about 45ns duration, by using an AND gate and applying the clock pulse directly to input ‘a’ but delaying its arrival at input ‘b’ by passing it through 3 inverters. This inverts the pulse and also delays it by three propagation delays, (about 15ns per inverter gate for 74HC series gates). The AND gate therefore produces logic 1 at its output only for the 45ns when both ‘a’ and ‘b’ are at logic 1 after the rising edge of the clock pulse.
A further refinement in Fig. 5.3.3 is the addition of two further inputs SET and RESET, which are actually the original S and Rinputs of the basic low activated SR flip-flop.
Notice that there is now a subtle difference between the active low Set and Reset inputs, and the D input. The D input is SYNCHRONOUS, that is its action is synchronised with the clock, but the inputs are ASYNCHRONOUS i.e. their action is NOT synchronised with the clock. The SET and RESET inputs in Fig 5.3.4 are ‘low activated’, which is shown by the inversion circles at the S and R inputs to indicate that they are really .
The flip-flop is positive edge triggered, which is shown on the CK input in Fig 5.3.4 by the wedge symbol. A wedge accompanied by an inversion circle would indicate negative (falling) edge triggering, though this is generally not used on D Type flip-flops.
The ‘Edge triggered D type flip-flop with asynchronous preset and clear capability’, although developed from the basic SR flip-flop becomes a very versatile flip-flop with many uses. A timing diagram illustrating the action of a positive edge triggered device is shown in Fig. 5.3.5.
At the positive going edges of clock pulses a and b, the D input is high so Q is also high.
Just before pulse c the D input goes low, so at the positive going edge of pulse c, Q goes low.
Between pulses c and d the asynchronous input goes low and immediately sets Q high.
The flip-flop then ignores pulse d while is low, but as returns high, and D has also returned to its high state before pulse e, Q remains high during pulse e.
At the positive going edge of pulse h, the low level of input D remains, keeping Q low, but between pulses h and i, the S input goes low, overriding any action of D and immediately making Q high.
D is still high at the positive going edge of pulse f, and because the flip-flop is positive edge triggered, the change in the logic level of D during pulse f is ignored until the positive going edge of pulse g, which resets Q to its low level.
Clock pulse i is again ignored, due to being in its active low state and Q remains high, under the control of until just before pulse j. At the positive going edge of pulse j, input D regains control, but as D is high and Q is already high, no change in output Q occurs.
Finally, just before pulse k, the asynchronous reset input goes low and resets Q to its low level (logic 0), which again causes the D input to be ignored.