The document DC Biasing BJTs (Part - 1) Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Analog Electronics.

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**DC Biasing - BJTs**

**Objectives To Understand :**

- Concept of Operating point and stability
- Analyzing Various biasing circuits and their comparison with respect to stability

**BJT – A Review**

- Invented in 1948 by Bardeen, Brattain and Shockley
- Contains three adjoining, alternately doped semiconductor regions: Emitter (E), Base (B), and Collector (C)
- The middle region, base, is very thin
- Emitter is heavily doped compared to collector. So, emitter and collector are not interchangeable.

**Three operating regions **

**Linear – region operation:**– Base – emitter junction forward biased – Base – collector junction reverse biased**Cutoff – region operation:**– Base – emitter junction reverse biased – Base – collector junction reverse biased**Saturation – region operation:**– Base – emitter junction forward biased – Base – collector junction forward biased

**Three operating regions of BJT **

**Cut off:**V_{CE}= V_{CC}, I_{C}≌ 0**Active or linear :**V_{CE}≌ V_{CC}/2 , I_{C}≌ I_{C}max/2**Saturation:**V_{CE}≌ 0 , I_{C}≌ I_{C}max

**Q-Point (Static Operation Point)**

- The values of the parameters I
_{B}, I_{C}and V_{CE }together are termed as „operating point‟ or Q ( Quiescent) point of the transistor.

**Q-Point**

- The intersection of the dc bias value of I
_{B}with the dc load line determines the Q-point. - It is desirable to have the Q-point centered on the load line. Why?
- When a circuit is designed to have a centered Q-point, the amplifier is said to be midpoint biased.
- Midpoint biasing allows optimum ac operation of the amplifier.

**Introduction - Biasing**

The analysis or design of a transistor amplifier requires knowledge of both the dc and ac response of the system.In fact, the amplifier increases the strength of a weak signal by transferring the energy from the applied DC source to the weak input ac signal

- The analysis or design of any electronic amplifier therefore has two components:
- The dc portion and
- The ac portion During the design stage, the choice of parameters for the required dc levels will affect the ac response.

**What is biasing circuit?**

- Once the desired dc current and voltage levels have been identified, a network must be constructed that will establish the desired values of I
_{B}, I_{C}and V_{CE}, Such a network is known as biasing circuit. A biasing network has to preferably make use of one power supply to bias both the junctions of the transistor.

**Purpose of the DC biasing circuit **

- To turn the device “ON”
- To place it in operation in the region of its characteristic where the device operates most linearly, i.e. to set up the initial dc values of I
_{B}, I_{C}, and V_{CE}

**Important basic relationship **

- V
_{BE}= 0.7V - I
_{E}= (b + 1) I_{B}≌ I_{C} - I
_{C}= β I_{B}

**Biasing circuits: **

- Fixed – bias circuit
- Emitter bias
- Voltage divider bias
- DC bias with voltage feedback
- Miscellaneous bias

**Fixed bias**

- The simplest transistor dc bias configuration.
- For dc analysis, open all the capacitance.

**DC Analysis**

- Applying KVL to the input loop:

VCC = I_{B}R_{B}+ V_{BE} - From the above equation, deriving for IB, we get,

I_{B}= [V_{CC}– V_{BE}] / R_{B} - The selection of RB sets the level of base current for the operating point.
- Applying KVL for the output loop:

V_{CC}= I_{C}R_{C}+ V_{CE} - Thus,

V_{CE} = V_{CC} – I_{C}R_{C}

- In circuits where emitter is grounded, V
_{CE}= V_{E}

V_{BE }= V_{B}

**Design and Analysis**

**Design:**Given – I_{B}, I_{C}, V_{CE}and V_{CC}, or I_{C}, V_{CE }and β, design the values of R_{B}, R_{C}using the equations obtained by applying KVL to input and output loops. "**Analysis:**Given the circuit values (V_{CC}, R_{B }and R_{C}), determine the values of I_{B}, I_{C}, V_{CE}using the equations obtained by applying KVL to input and output loops.

**Problem – Analysis**

Given the fixed bias circuit with V_{CC} = 12V, R_{B} = 240 kΩ, R_{C} = 2.2 kΩ and β = 75. Determine the values of operating point.

Equation for the input loop is: I_{B} = [V_{CC} – V_{BE]} / R_{B} where V_{BE} = 0.7V, thus substituting the other given values in the equation, we get

I_{B} = 47.08uA

I_{C} = b_{IB} = 3.53mA

V_{CE} = V_{CC} - I_{C}R_{C }= 4.23V

- When the transistor is biased such that IB is very high so as to make I
_{C}very high such that I_{C}R_{C}drop is almost V_{CC}and V_{CE}is almost 0, the transistor is said to be in saturation. I_{C}sat = V_{CC}/ R_{C}in a fixed bias circuit.

**Verification**

- Whenever a fixed bias circuit is analyzed, the value of I
_{CQ}obtained could be verified with the value of I_{CSat }( = V_{CC}/ R_{C}) to understand whether the transistor is in active region. - In active region,

I_{CQ }= ( I_{CSat} /2)

**Load line analysis**

A fixed bias circuit with given values of V_{CC}, R_{C} and R_{B} can be analyzed ( means, determining the values of I_{BQ}, I_{CQ} and V_{CEQ}) using the concept of load line also. Here the input loop KVL equation is not used for the purpose of analysis, instead, the output characteristics of the transistor used in the given circuit and output loop KVL equation are made use of.

- The method of load line analysis is as below:

1. Consider the equation V_{CE}= V_{CC}– I_{C}R_{C}This relates V_{CE}and I_{C}for the given I_{B}and R_{C}

2. Also, we know that, V_{CE}and I_{C}are related through output characteristics We know that the equation, V_{CE}= V_{CC}– I_{C}R_{C}represents a straight line which can be plotted on the output characteristics of the transistor.

Such line drawn as per the above equation is known as load line, the slope of which is decided by the value of RC ( the load).

**Load line**

- The two extreme points on the load line can be calculated and by joining which the load line can be drawn.
- To find extreme points, first, Ic is made 0 in the equation: V
_{CE}= V_{CC}– I_{C}R_{C}. This gives the coordinates (V_{CC},0) on the x axis of the output characteristics. - The other extreme point is on the y-axis and can be calculated by making V
_{CE}= 0 in the equation V_{CE}= V_{CC}– I_{C}R_{C}which gives I_{C}( max) = V_{CC}/ R_{C}thus giving the coordinates of the point as (0, V_{CC}/ R_{C}). - The two extreme points so obtained are joined to form the load line.
- The load line intersects the output characteristics at various points corresponding to different I
_{B}s. The actual operating point is established for the given I_{B}.

**Q point variation**

As I_{B} is varied, the Q point shifts accordingly on the load line either up or down depending on I_{B} increased or decreased respectively.

As R_{C} is varied, the Q point shifts to left or right along the same I_{B} line since the slope of the line varies. As R_{C} increases, slope reduces ( slope is -1/R_{C}) which results in shift of Q point to the left meaning no variation in I_{C} and reduction in V_{CE} . Thus if the output characteristics is known, the analysis of the given fixed bias circuit or designing a fixed bias circuit is possible using load line analysis as mentioned above.

**Emitter Bias**

- It can be shown that, including an emitter resistor in the fixed bias circuit improves the stability of Q point.
- Thus emitter bias is a biasing circuit very similar to fixed bias circuit with an emitter resistor added to it.

**Input loop**

- Writing KVL around the input loop we get, V
_{CC}= I_{B}R_{B}+ V_{BE}+ I_{E}R_{E }(1)

We know that,

IE = (β+1)I_{B} (2)

Substituting this in (1), we get,

V_{CC} = I_{B}R_{B} + V_{BE} + (b+1)I_{B}R_{E}

V_{CC} – V_{BE} = I_{B}(R_{B} + (b+1) R_{E})

Solving for I_{B}:

I_{B} = (V_{CC} – V_{BE} ) /[(R_{B} + (b+1) R_{E})]

The expression for I_{B} in a fixed bias circuit was, I_{B} = (V_{CC} – V_{BE} ) /R,

**Equivalent input loop:**

- R
_{EI}in the above circuit is (β +1)R_{E}which means that, the emitter resistance that is common to both the loops appears as such a high resistance in the input loop. " Thus R_{i }= (β+1)R_{E}( more about this when we take up ac analysis)

**Output loop**

Collector – emitter loop Applying KVL,

V_{CC} = I_{C}R_{C} + V_{CE} + I_{E}R_{E}

I_{C} is almost same as I_{E}

Thus,

V_{CC} = I_{C}R_{C} + V_{CE} + I_{C}R_{E}

= I_{C} (R_{C} + R_{E}) +V_{CE}

V_{CE }= V_{CC} - I_{C} (R_{C} + R_{E})

Since emitter is not connected directly to ground, it is at a potential V_{E}, given by,

V_{E} = I_{E}R_{E}

V_{C} = V_{CE} + V_{E} OR V_{C} = V_{CC }– I_{C}R_{C}

Also, V_{B} = V_{CC} – I_{B}R_{B} OR V_{B} = V_{BE} + V_{E}

**Problem:**

**Analyze the following circuit: **given b = 75, V_{CC} = 16V, R_{B} = 430kΩ, R_{C }= 2kΩ and R_{E} = 1k Ω

**Solution:**

I_{B} = (V_{CC} – V_{BE} ) /[(R_{B} + (b+1) R_{E})]

= ( 16 – 0.7) / [ 430k + (76) 1k] = 30.24mA I_{C} = ( 75) (30.24mA) = 2.27mA V_{CE} = V_{CC} - I_{C} (R_{C} + R_{E}) = 9.19V

V_{C }= V_{CC} – I_{C}R_{C} = 11.46V

V_{E} = V_{C} – V_{CE} = 2.27V

V_{B} = V_{BE} + V_{E} = 2.97V

V_{BC }= V_{B} – V_{C} = 2.97 – 11.46 = - 8.49V

8 videos|20 docs|22 tests

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- Doc | 5 pages
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### Test: Operating Point Of Transistor

- Test | 10 ques | 10 min
### DC Biasing BJTs (Part - 3)

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### Transistor Biasing

- Video | 23:53 min
### Test: Characteristics Of Amplifier

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