Detailed Notes: Differential Amplifiers | Analog Circuits - Electronics and Communication Engineering (ECE) PDF Download

 Page 1


1 MOS Dierential Amplier, Cont.
1.1 Small-Signal Analysis
To operate the dierential amplier in the linear regime, it has to operate with
small signal input. Figure 1(a) is the dierential amplifer with a small signal
superimposed on top of at DC common-mode signal V
CM
. The input signals
are
v
G1
=V
CM
+
1
2
v
id
; v
G2
=V
CM

1
2
v
id
(1.1)
Then without loss of generality, one can set V
CM
= 0, and get the small signal
model shown in Figure 1(b). The transistor circuit can be further simplied
with T-model equivalent circuit to arrive at Figure 1(c).
The dierential input signal is applied in an anti-symmetric or comple-
mentary manner as shown. Also, by symmetry, because of the way the am-
plier is driven by anti-symmetric signals, the voltage midway between the two
ampliers must be zero making a virtual ground.
From (7.42) of Sedra and Smith, or from (3.4) of Oct 24, 2017 lecture,
g
m
=
2I
D
V
OV
=
2(I=2)
V
OV
=
I
V
OV
(1.2)
Notice that due to symmetry, a virtual ground is established at the location of
the original current source. Finally, using the transconductance, one obtains
that
v
o1
=g
m
v
id
2
R
D
; v
o2
= +g
m
v
id
2
R
D
(1.3)
v
o1
v
id
=
1
2
g
m
R
D
;
v
o2
v
id
= +
1
2
g
m
R
D
(1.4)
Or when the dierential output is taken, the dierential voltage gain proper is
A
d
=
v
od
v
id
=
v
o2
v
o1
v
id
=g
m
R
D
(1.5)
Printed on November 7, 2017 at 15:14: W.C. Chew and Z.H. Chen.
Page 2


1 MOS Dierential Amplier, Cont.
1.1 Small-Signal Analysis
To operate the dierential amplier in the linear regime, it has to operate with
small signal input. Figure 1(a) is the dierential amplifer with a small signal
superimposed on top of at DC common-mode signal V
CM
. The input signals
are
v
G1
=V
CM
+
1
2
v
id
; v
G2
=V
CM

1
2
v
id
(1.1)
Then without loss of generality, one can set V
CM
= 0, and get the small signal
model shown in Figure 1(b). The transistor circuit can be further simplied
with T-model equivalent circuit to arrive at Figure 1(c).
The dierential input signal is applied in an anti-symmetric or comple-
mentary manner as shown. Also, by symmetry, because of the way the am-
plier is driven by anti-symmetric signals, the voltage midway between the two
ampliers must be zero making a virtual ground.
From (7.42) of Sedra and Smith, or from (3.4) of Oct 24, 2017 lecture,
g
m
=
2I
D
V
OV
=
2(I=2)
V
OV
=
I
V
OV
(1.2)
Notice that due to symmetry, a virtual ground is established at the location of
the original current source. Finally, using the transconductance, one obtains
that
v
o1
=g
m
v
id
2
R
D
; v
o2
= +g
m
v
id
2
R
D
(1.3)
v
o1
v
id
=
1
2
g
m
R
D
;
v
o2
v
id
= +
1
2
g
m
R
D
(1.4)
Or when the dierential output is taken, the dierential voltage gain proper is
A
d
=
v
od
v
id
=
v
o2
v
o1
v
id
=g
m
R
D
(1.5)
Printed on November 7, 2017 at 15:14: W.C. Chew and Z.H. Chen.
Figure 1: Small-signl analysis of the MOS dierential amplier: (a) The circuit
with DC biases in place. (b) The small-signal circuit of the dierential amplier
with DC biased removed. (c) The T-model equivalent circuit of the dierential
amplier (Courtesy of Sedra and Smith).
Page 3


1 MOS Dierential Amplier, Cont.
1.1 Small-Signal Analysis
To operate the dierential amplier in the linear regime, it has to operate with
small signal input. Figure 1(a) is the dierential amplifer with a small signal
superimposed on top of at DC common-mode signal V
CM
. The input signals
are
v
G1
=V
CM
+
1
2
v
id
; v
G2
=V
CM

1
2
v
id
(1.1)
Then without loss of generality, one can set V
CM
= 0, and get the small signal
model shown in Figure 1(b). The transistor circuit can be further simplied
with T-model equivalent circuit to arrive at Figure 1(c).
The dierential input signal is applied in an anti-symmetric or comple-
mentary manner as shown. Also, by symmetry, because of the way the am-
plier is driven by anti-symmetric signals, the voltage midway between the two
ampliers must be zero making a virtual ground.
From (7.42) of Sedra and Smith, or from (3.4) of Oct 24, 2017 lecture,
g
m
=
2I
D
V
OV
=
2(I=2)
V
OV
=
I
V
OV
(1.2)
Notice that due to symmetry, a virtual ground is established at the location of
the original current source. Finally, using the transconductance, one obtains
that
v
o1
=g
m
v
id
2
R
D
; v
o2
= +g
m
v
id
2
R
D
(1.3)
v
o1
v
id
=
1
2
g
m
R
D
;
v
o2
v
id
= +
1
2
g
m
R
D
(1.4)
Or when the dierential output is taken, the dierential voltage gain proper is
A
d
=
v
od
v
id
=
v
o2
v
o1
v
id
=g
m
R
D
(1.5)
Printed on November 7, 2017 at 15:14: W.C. Chew and Z.H. Chen.
Figure 1: Small-signl analysis of the MOS dierential amplier: (a) The circuit
with DC biases in place. (b) The small-signal circuit of the dierential amplier
with DC biased removed. (c) The T-model equivalent circuit of the dierential
amplier (Courtesy of Sedra and Smith).
Figure 2: Alternative view of the small-signal analysis where (a) the analysis is
done directly on the circuit, (b) the analysis is done on the T-model equivalent
circuit (Courtesy of Sedra and Smith).
Figure 3: The equivalent dierential half-circuit of the model shown in Figure
2(a) (Courtesy of Sedra and Smith).
Page 4


1 MOS Dierential Amplier, Cont.
1.1 Small-Signal Analysis
To operate the dierential amplier in the linear regime, it has to operate with
small signal input. Figure 1(a) is the dierential amplifer with a small signal
superimposed on top of at DC common-mode signal V
CM
. The input signals
are
v
G1
=V
CM
+
1
2
v
id
; v
G2
=V
CM

1
2
v
id
(1.1)
Then without loss of generality, one can set V
CM
= 0, and get the small signal
model shown in Figure 1(b). The transistor circuit can be further simplied
with T-model equivalent circuit to arrive at Figure 1(c).
The dierential input signal is applied in an anti-symmetric or comple-
mentary manner as shown. Also, by symmetry, because of the way the am-
plier is driven by anti-symmetric signals, the voltage midway between the two
ampliers must be zero making a virtual ground.
From (7.42) of Sedra and Smith, or from (3.4) of Oct 24, 2017 lecture,
g
m
=
2I
D
V
OV
=
2(I=2)
V
OV
=
I
V
OV
(1.2)
Notice that due to symmetry, a virtual ground is established at the location of
the original current source. Finally, using the transconductance, one obtains
that
v
o1
=g
m
v
id
2
R
D
; v
o2
= +g
m
v
id
2
R
D
(1.3)
v
o1
v
id
=
1
2
g
m
R
D
;
v
o2
v
id
= +
1
2
g
m
R
D
(1.4)
Or when the dierential output is taken, the dierential voltage gain proper is
A
d
=
v
od
v
id
=
v
o2
v
o1
v
id
=g
m
R
D
(1.5)
Printed on November 7, 2017 at 15:14: W.C. Chew and Z.H. Chen.
Figure 1: Small-signl analysis of the MOS dierential amplier: (a) The circuit
with DC biases in place. (b) The small-signal circuit of the dierential amplier
with DC biased removed. (c) The T-model equivalent circuit of the dierential
amplier (Courtesy of Sedra and Smith).
Figure 2: Alternative view of the small-signal analysis where (a) the analysis is
done directly on the circuit, (b) the analysis is done on the T-model equivalent
circuit (Courtesy of Sedra and Smith).
Figure 3: The equivalent dierential half-circuit of the model shown in Figure
2(a) (Courtesy of Sedra and Smith).
An alternative way of viewing the above analysis is to use the model shown
in Figure 2. When a total voltage v
id
is applied between gates G
1
and G
2
,
then the impedance seen by this voltage is 2=g
m
. And the current produced
is (g
m
=2)v
id
, and the voltage v
o1
=g
m
R
D
=2, giving the same result as seen
before.
1.1.1 The Dierential Half-Circuit
Due to the symmetry of the dierential amplier, a virtual ground can be in-
serted right in between the two transistors: hence, only a half circuit needs to
be analyzed as shown in Figure 3. Then the dierential gain is given by
A
d
=g
m
(R
D
kr
o
) (1.6)
where we have assumed the presence of an output resistor r
o
to account for the
Early eect.
1.1.2 Dierential Amplier with Current-Source Loads
A MOSFET without the Early eect behaves like a current source because
changes in V
DS
does not change I
D
. Hence, an appropriately biased MOSFET
with the correct gate voltage can be used as a current source. Thus, the load
of the dierential amplier can be replaced with a current source which ideally
has an innite internal impedance. Figure 4(a) shows the realization of such
current sources with PMOS Q
3
and Q
4
.
1
The bias voltage V
G
is chosen to
ensure a drain current equal to I=2. Due to the symmetry of the design, the
half-circuit is shown in Figre 4(b). Therefore, the dierential gain is given by
A
d
=
v
od
v
id
=g
m1
(r
o1
kr
o3
) (1.7)
where the R
D
in (1.6) is now replaced by r
o3
.
2 BJT Dierential Pair
The basic conguration of the BJT dierential pair is shown in Figure 5, which
is very similar to the MOSFET dierential pair. Here it is assumed that the
transistors are in active mode and not in saturation mode
2
2.1 Basic Operation
Again, the basic operation of the dierential pair is divided into the common
mode operation plus a dierential mode operation. In other words,
v
B1
=
1
2
(v
B1
+v
B2
) +
1
2
(v
B1
v
B2
); v
B2
=
1
2
(v
B1
+v
B2
)
1
2
(v
B1
v
B2
)
(2.1)
1
They could equally have been realized with NMOS.
2
Please note that saturation for BJT is very dierent in meaning from saturation for
MOSFET.
Page 5


1 MOS Dierential Amplier, Cont.
1.1 Small-Signal Analysis
To operate the dierential amplier in the linear regime, it has to operate with
small signal input. Figure 1(a) is the dierential amplifer with a small signal
superimposed on top of at DC common-mode signal V
CM
. The input signals
are
v
G1
=V
CM
+
1
2
v
id
; v
G2
=V
CM

1
2
v
id
(1.1)
Then without loss of generality, one can set V
CM
= 0, and get the small signal
model shown in Figure 1(b). The transistor circuit can be further simplied
with T-model equivalent circuit to arrive at Figure 1(c).
The dierential input signal is applied in an anti-symmetric or comple-
mentary manner as shown. Also, by symmetry, because of the way the am-
plier is driven by anti-symmetric signals, the voltage midway between the two
ampliers must be zero making a virtual ground.
From (7.42) of Sedra and Smith, or from (3.4) of Oct 24, 2017 lecture,
g
m
=
2I
D
V
OV
=
2(I=2)
V
OV
=
I
V
OV
(1.2)
Notice that due to symmetry, a virtual ground is established at the location of
the original current source. Finally, using the transconductance, one obtains
that
v
o1
=g
m
v
id
2
R
D
; v
o2
= +g
m
v
id
2
R
D
(1.3)
v
o1
v
id
=
1
2
g
m
R
D
;
v
o2
v
id
= +
1
2
g
m
R
D
(1.4)
Or when the dierential output is taken, the dierential voltage gain proper is
A
d
=
v
od
v
id
=
v
o2
v
o1
v
id
=g
m
R
D
(1.5)
Printed on November 7, 2017 at 15:14: W.C. Chew and Z.H. Chen.
Figure 1: Small-signl analysis of the MOS dierential amplier: (a) The circuit
with DC biases in place. (b) The small-signal circuit of the dierential amplier
with DC biased removed. (c) The T-model equivalent circuit of the dierential
amplier (Courtesy of Sedra and Smith).
Figure 2: Alternative view of the small-signal analysis where (a) the analysis is
done directly on the circuit, (b) the analysis is done on the T-model equivalent
circuit (Courtesy of Sedra and Smith).
Figure 3: The equivalent dierential half-circuit of the model shown in Figure
2(a) (Courtesy of Sedra and Smith).
An alternative way of viewing the above analysis is to use the model shown
in Figure 2. When a total voltage v
id
is applied between gates G
1
and G
2
,
then the impedance seen by this voltage is 2=g
m
. And the current produced
is (g
m
=2)v
id
, and the voltage v
o1
=g
m
R
D
=2, giving the same result as seen
before.
1.1.1 The Dierential Half-Circuit
Due to the symmetry of the dierential amplier, a virtual ground can be in-
serted right in between the two transistors: hence, only a half circuit needs to
be analyzed as shown in Figure 3. Then the dierential gain is given by
A
d
=g
m
(R
D
kr
o
) (1.6)
where we have assumed the presence of an output resistor r
o
to account for the
Early eect.
1.1.2 Dierential Amplier with Current-Source Loads
A MOSFET without the Early eect behaves like a current source because
changes in V
DS
does not change I
D
. Hence, an appropriately biased MOSFET
with the correct gate voltage can be used as a current source. Thus, the load
of the dierential amplier can be replaced with a current source which ideally
has an innite internal impedance. Figure 4(a) shows the realization of such
current sources with PMOS Q
3
and Q
4
.
1
The bias voltage V
G
is chosen to
ensure a drain current equal to I=2. Due to the symmetry of the design, the
half-circuit is shown in Figre 4(b). Therefore, the dierential gain is given by
A
d
=
v
od
v
id
=g
m1
(r
o1
kr
o3
) (1.7)
where the R
D
in (1.6) is now replaced by r
o3
.
2 BJT Dierential Pair
The basic conguration of the BJT dierential pair is shown in Figure 5, which
is very similar to the MOSFET dierential pair. Here it is assumed that the
transistors are in active mode and not in saturation mode
2
2.1 Basic Operation
Again, the basic operation of the dierential pair is divided into the common
mode operation plus a dierential mode operation. In other words,
v
B1
=
1
2
(v
B1
+v
B2
) +
1
2
(v
B1
v
B2
); v
B2
=
1
2
(v
B1
+v
B2
)
1
2
(v
B1
v
B2
)
(2.1)
1
They could equally have been realized with NMOS.
2
Please note that saturation for BJT is very dierent in meaning from saturation for
MOSFET.
Figure 4: (a) Dierential amplier where the load is replaced by a current source
approximated by MOSFETs Q
3
and Q
4
. (b) The dierential half circuit of (a)
(Courtesy of Sedra and Smith).