Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

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Electrical Engineering (EE) : Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

The document Field Effect Transistor Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Electronic Devices.
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INTRODUCTION

  1. The Field effect transistor abbreviated as FET , is an another semiconductor device like a BJT  which can be used as an amplifier or a switch.
  2. The Field effect transistor is a voltage operated device. Whereas Bipolar junction transistor is a current controlled device. Unlike BJT a FET requires virtually no input current.
  3. This gives it an extremely high input resistance , which is its most important advantage over a bipolar transistor.
  4. FET is also a three terminal device, labelled  as source, drain and gate.
  5. The source can be viewed as BJT’s emitter, the drain as collector, and the gate as the counter part of the base.
  6. The material that connects the source to drain is referred to as the channel.
  7. FET operation depends only on the flow of majority carriers ,therefore they are called uni polar  devices. BJT operation depends on both minority and majority carriers.
  8. As FET has conduction through only majority carriers it is less noisy than BJT.
  9. FETs are much easier to fabricate and are particularly suitable for ICs because they occupy less space than BJTs.
  10. FET amplifiers have low gain bandwidth product due to the junction capacitive effects and produce more signal distortion except for small signal operation.
  11. The performance of FET is relatively unaffected by ambient temperature changes. As it has a negative temperature coefficient at high current levels, it prevents the FET from thermal breakdown. The BJT has a positive temperature coefficient at high current levels which leads to thermal breakdown.

6.2 CLASSIFICATION OF FET:

There are two major categories of field effect transistors:

1. Junction Field Effect Transistors

2. MOSFETs

These are further sub-divided in to P- channel and N-channel devices.

MOSFETs are further classified  into two types: Depletion MOSFETs  and Enhancement MOSFETs

When the channel is of N-type the JFET is referred to as an N-channel JFET ,when the channel is of P-type the JFET is referred to as P-channel JFET.

The schematic symbols for the P-channel and N-channel JFETs are shown in the figure.

          Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

CONSTRUCTION AND OPERATION OF N- CHANNEL FET

If the gate is a N-type material, the channel must be a P-type material.

CONSTRUCTION OF N-CHANNEL JFET:

             Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

A piece of N- type material, referred to as channel has two smaller pieces of P-type material attached to its sides, forming PN junctions. The  channel ends are designated as the drain and source . And the two pieces of P-type material are connected together and their terminal is called the gate. Since this channel is in the N-type bar, the FET is known as N-channel JFET.

OPERATION OF N-CHANNEL JFET:-  

The overall operation of the JFET is based on varying the width of the channel to control the drain current.

    A piece of N-type material referred to as the channel, has two smaller pieces of P-type material attached to its sites, forming PN-Junctions. The channel’s ends are designated the drain and the source. And the two pieces of P-type material are connected together and their terminal is called the gate. With the gate terminal not connected and the potential applied positive at the drain and negative at the source, a drain current Id flows. When the gate is biased negative with respect to the source, the PN junctions are reverse biased and depletion regions are formed. The channel is more lightly doped than the P-type gate blocks, so the depletion regions penetrate deeply into the channel. Since depletion region is a region with less no. of charge carriers so it behaves as an insulator. The result is that the channel is narrowed. Its resistance is increased and Id is reduced. When the negative gate bias voltage is further increased, the depletion regions meet at the center and Id is cut off completely.

There are two ways to control the channel width

  1. By varying the value of Vgs
  2. And by Varying the value of Vds  holding Vgs constant

1 By varying the value of Vgs :- 

         We can vary the width of the channel and in turn vary the amount of drain current. This can be done by varying the value of Vgs. This point is illustrated in the fig  below. Here we are dealing with N-channel FET. So channel is of N-type and gate is of P-type that constitutes a PN junction. This PN junction is always reverse biased in JFET operation .The reverse bias is applied by a battery voltage Vgs connected between the gate and the source terminal i.e positive terminal of the battery is connected to the source and negative terminal to gate.

Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

  1. When a PN junction is reverse biased the electrons and holes diffuse across junction by leaving immobile ions on the N and P sides , the region containing these immobile ions  is known as depletion region.
  2. If both P and N regions are heavily doped then the depletion region extends symmetrically on both sides.
  3. But in N-channel FET P region is heavily doped than N-type thus depletion region extends more in N region than P region.
  4. So when no Vds is applied the depletion region is symmetrical and the conductivity becomes zero. Since there are no mobile carriers in the junction.
  5. As the reverse bias voltage increases the thickness of the depletion region also increases.  i.e. the effective channel width decreases .
  6. By varying the value of Vgs we can vary the width of the channel.

 

2 Varying the value of Vds  holding Vgs constant :-

Field Effect Transistor Electrical Engineering (EE) Notes | EduRev               Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

  1. When no voltage is applied to the gate i.e. Vgs=0 , Vds is applied between source and drain the electrons will flow from source to drain through the channel constituting drain current Id .
  2. With Vgs= 0 for Id= 0, the channel between the gate junctions is entirely open. In response to a small applied voltage Vds , the entire bar acts as a simple semi-conductor resistor and the current Id increases linearly with Vds .
  3. The channel resistances are represented as rd and rs as shown in the fig above.
  4. This increasing drain current Id produces a voltage drop across rd which reverse biases the gate to source junction,(rd> rs). Thus the depletion region is formed which is not symmetrical .
  5. The depletion region developed penetrates deeper into the channel near drain and less towards source because Vrd >> Vrs. So reverse bias is higher near drain than at source.
  6. As a result, growing depletion region reduces the effective width of the channel. Eventually a voltage Vds is reached at which the channel is pinched off. This is the voltage where the current Id begins to level off and approach a constant value.
  7.  So, by varying the value of Vds we can vary the width of the channel holding Vgs constant.

When both Vgs and Vds is applied:-

Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

          It is of course in principle not possible for the channel to close completely and thereby reduce the current Id to zero,  if such indeed, could be the case the gate voltage Vgs is applied in the direction to provide additional reverse bias.

Field Effect Transistor Electrical Engineering (EE) Notes | EduRev

  1. When voltage is applied between the drain and source with a battery Vdd, the electrons flow from source to drain through the narrow channel existing between the depletion regions. This constitutes the drain current Id, its conventional direction is from drain to source.
  2. The value of drain current is maximum when no external voltage is applied between gate and source and is designated by Idss.
  3. When Vgs is increased beyond zero the depletion regions are widened. This reduces the effective width of the channel and therefore controls the flow of drain current through the channel.
  4. When Vgs is further increased a stage is reached at which to depletion regions touch each other that means the entire channel is closed with depletion region. This reduces the drain current to zero.
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