Flip-flops - PowerPoint Presentation, Electronics Engineering, Semester

# Flip-flops - PowerPoint Presentation, Electronics Engineering, Semester

``` Page 1

October 15, 2003 Flip-flops 1
Flip-Flops
• Last time, we saw how latches can be used as memory in a circuit.
• Latches introduce new problems:
– We need to know when to enable a latch.
– We also need to quickly disable a latch.
– In other words, it’s difficult to control the timing of latches in a
large circuit.
• We solve these problems with two new elements: clocks and flip-flops
– Clocks tell us when to write to our memory.
– Flip-flops allow us to quickly write the memory at clearly defined
times.
– Used together, we can create circuits without worrying about the
memory timing.

Page 2

October 15, 2003 Flip-flops 1
Flip-Flops
• Last time, we saw how latches can be used as memory in a circuit.
• Latches introduce new problems:
– We need to know when to enable a latch.
– We also need to quickly disable a latch.
– In other words, it’s difficult to control the timing of latches in a
large circuit.
• We solve these problems with two new elements: clocks and flip-flops
– Clocks tell us when to write to our memory.
– Flip-flops allow us to quickly write the memory at clearly defined
times.
– Used together, we can create circuits without worrying about the
memory timing.

October 15, 2003 Flip-flops 2
An SR latch with a control input
• Here is an SR latch with a control input C.

• Notice the hierarchical design!
– The dotted blue box is the S’R’ latch.
– The additional NAND gates are simply used to generate the correct
inputs for the S’R’ latch.
• The control input acts just like an enable.
C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
Page 3

October 15, 2003 Flip-flops 1
Flip-Flops
• Last time, we saw how latches can be used as memory in a circuit.
• Latches introduce new problems:
– We need to know when to enable a latch.
– We also need to quickly disable a latch.
– In other words, it’s difficult to control the timing of latches in a
large circuit.
• We solve these problems with two new elements: clocks and flip-flops
– Clocks tell us when to write to our memory.
– Flip-flops allow us to quickly write the memory at clearly defined
times.
– Used together, we can create circuits without worrying about the
memory timing.

October 15, 2003 Flip-flops 2
An SR latch with a control input
• Here is an SR latch with a control input C.

• Notice the hierarchical design!
– The dotted blue box is the S’R’ latch.
– The additional NAND gates are simply used to generate the correct
inputs for the S’R’ latch.
• The control input acts just like an enable.
C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
October 15, 2003 Flip-flops 3
D latch
• Finally, a D latch is based on an S’R’ latch. The additional gates generate
the S’ and R’ signals, based on inputs D (“data”) and C (“control”).
– When C = 0, S’ and R’ are both 1, so the state Q does not change.
– When C = 1, the latch output Q will equal the input D.
• No more messing with one input for set and another input for reset!

• Also, this latch has no “bad” input combinations to avoid. Any of the
four possible assignments to C and D are valid.

C D Q
0 x No change
1 0 0
1 1 1
Page 4

October 15, 2003 Flip-flops 1
Flip-Flops
• Last time, we saw how latches can be used as memory in a circuit.
• Latches introduce new problems:
– We need to know when to enable a latch.
– We also need to quickly disable a latch.
– In other words, it’s difficult to control the timing of latches in a
large circuit.
• We solve these problems with two new elements: clocks and flip-flops
– Clocks tell us when to write to our memory.
– Flip-flops allow us to quickly write the memory at clearly defined
times.
– Used together, we can create circuits without worrying about the
memory timing.

October 15, 2003 Flip-flops 2
An SR latch with a control input
• Here is an SR latch with a control input C.

• Notice the hierarchical design!
– The dotted blue box is the S’R’ latch.
– The additional NAND gates are simply used to generate the correct
inputs for the S’R’ latch.
• The control input acts just like an enable.
C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
October 15, 2003 Flip-flops 3
D latch
• Finally, a D latch is based on an S’R’ latch. The additional gates generate
the S’ and R’ signals, based on inputs D (“data”) and C (“control”).
– When C = 0, S’ and R’ are both 1, so the state Q does not change.
– When C = 1, the latch output Q will equal the input D.
• No more messing with one input for set and another input for reset!

• Also, this latch has no “bad” input combinations to avoid. Any of the
four possible assignments to C and D are valid.

C D Q
0 x No change
1 0 0
1 1 1
October 15, 2003 Flip-flops 4
Using latches in real life
• We can connect some latches, acting as memory, to an ALU.

• Let’s say these latches contain some value that we want to increment.
– The ALU should read the current latch value.
– It applies the “G = X + 1” operation.
– The incremented value is stored back into the latches.
• At this point, we have to stop the cycle, so the latch value doesn’t get
incremented again by accident.
• One convenient way to break the loop is to disable the latches.
+1
ALU
S
X
G
Latches
D
Q
C
Page 5

October 15, 2003 Flip-flops 1
Flip-Flops
• Last time, we saw how latches can be used as memory in a circuit.
• Latches introduce new problems:
– We need to know when to enable a latch.
– We also need to quickly disable a latch.
– In other words, it’s difficult to control the timing of latches in a
large circuit.
• We solve these problems with two new elements: clocks and flip-flops
– Clocks tell us when to write to our memory.
– Flip-flops allow us to quickly write the memory at clearly defined
times.
– Used together, we can create circuits without worrying about the
memory timing.

October 15, 2003 Flip-flops 2
An SR latch with a control input
• Here is an SR latch with a control input C.

• Notice the hierarchical design!
– The dotted blue box is the S’R’ latch.
– The additional NAND gates are simply used to generate the correct
inputs for the S’R’ latch.
• The control input acts just like an enable.
C S R S’ R’ Q
0 x x 1 1 No change
1 0 0 1 1 No change
1 0 1 1 0 0 (reset)
1 1 0 0 1 1 (set)
1 1 1 0 0 Avoid!
October 15, 2003 Flip-flops 3
D latch
• Finally, a D latch is based on an S’R’ latch. The additional gates generate
the S’ and R’ signals, based on inputs D (“data”) and C (“control”).
– When C = 0, S’ and R’ are both 1, so the state Q does not change.
– When C = 1, the latch output Q will equal the input D.
• No more messing with one input for set and another input for reset!

• Also, this latch has no “bad” input combinations to avoid. Any of the
four possible assignments to C and D are valid.

C D Q
0 x No change
1 0 0
1 1 1
October 15, 2003 Flip-flops 4
Using latches in real life
• We can connect some latches, acting as memory, to an ALU.

• Let’s say these latches contain some value that we want to increment.
– The ALU should read the current latch value.
– It applies the “G = X + 1” operation.
– The incremented value is stored back into the latches.
• At this point, we have to stop the cycle, so the latch value doesn’t get
incremented again by accident.
• One convenient way to break the loop is to disable the latches.
+1
ALU
S
X
G
Latches
D
Q
C
October 15, 2003 Flip-flops 5
The problem with latches

• The problem is exactly when to disable the latches. You have to wait
long enough for the ALU to produce its output, but no longer.
– But different ALU operations have different delays. For instance,
arithmetic operations might go through an adder, whereas logical
operations don’t.
– Changing the ALU implementation, such as using a carry-lookahead
• In general, it’s very difficult to know how long operations take, and how
long latches should be enabled for.

+1
ALU
S
X
G
Latches
D
Q
C
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