Formula sheet: Counters and Shift Registers | Digital Circuits - Electronics and Communication Engineering (ECE) PDF Download

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Digital Circuits: Coun ters & Shift Registers F orm ula
Sheet for GA TE
Coun ters
• Definition : A coun ter is a sequen tial circuit that coun ts pulses in a sp ecific sequence.
• T yp es of Coun ters :
– Async hronous (Ripple) Coun ter : Flip-flops are triggered sequen tially , caus-
ing a ripple effect.
– Sync hronous Coun ter : All flip-flops are triggered sim ultaneously b y a common
clo c k.
• Mo dulus of Coun ter : Num b er of unique states in the coun ting sequence.
Mo dulus =N ( for an n -bit coun ter, N = 2
n
)
• F requency Division : Output frequency of a coun ter.
f
out
=
f
in
N
where f
in
is the input clo c k frequency , N is the mo dulus.
• Maxim um Coun t : F or an n -bit binary coun ter.
Max Coun t = 2
n
-1
• State T ransition : Determined b y flip-flop excitation tables (e.g., JK, D, T flip-flops).
F or JK Flip-Flop :J =K = 1 (toggle), J =K = 0 (no c hange)
F or D Flip-Flop :Q
next
=D
F or T Flip-Flop :Q
next
=Q?T
• Up/Do wn Coun ter :
Up Coun t :Q
next
=Q+1, Do wn Coun t :Q
next
=Q-1
Shift Registers
• Definition : A sequen tial circuit that shifts data bits left or righ t with eac h clo c k
pulse.
• T yp es of Shift Registers :
– SISO (Serial In, Serial Out) : Data en ters and exits serially .
– SIPO (Serial In, P arallel Out) : Data en ters serially , exits in parallel.
– PISO (P arallel In, Serial Out) : Data en ters in parallel, exits serially .
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Page 2


Digital Circuits: Coun ters & Shift Registers F orm ula
Sheet for GA TE
Coun ters
• Definition : A coun ter is a sequen tial circuit that coun ts pulses in a sp ecific sequence.
• T yp es of Coun ters :
– Async hronous (Ripple) Coun ter : Flip-flops are triggered sequen tially , caus-
ing a ripple effect.
– Sync hronous Coun ter : All flip-flops are triggered sim ultaneously b y a common
clo c k.
• Mo dulus of Coun ter : Num b er of unique states in the coun ting sequence.
Mo dulus =N ( for an n -bit coun ter, N = 2
n
)
• F requency Division : Output frequency of a coun ter.
f
out
=
f
in
N
where f
in
is the input clo c k frequency , N is the mo dulus.
• Maxim um Coun t : F or an n -bit binary coun ter.
Max Coun t = 2
n
-1
• State T ransition : Determined b y flip-flop excitation tables (e.g., JK, D, T flip-flops).
F or JK Flip-Flop :J =K = 1 (toggle), J =K = 0 (no c hange)
F or D Flip-Flop :Q
next
=D
F or T Flip-Flop :Q
next
=Q?T
• Up/Do wn Coun ter :
Up Coun t :Q
next
=Q+1, Do wn Coun t :Q
next
=Q-1
Shift Registers
• Definition : A sequen tial circuit that shifts data bits left or righ t with eac h clo c k
pulse.
• T yp es of Shift Registers :
– SISO (Serial In, Serial Out) : Data en ters and exits serially .
– SIPO (Serial In, P arallel Out) : Data en ters serially , exits in parallel.
– PISO (P arallel In, Serial Out) : Data en ters in parallel, exits serially .
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– PIPO (P arallel In, P arallel Out) : Data en ters and exits in parallel.
• Shift Op eration : F or an n -bit shift register, data shifts b y one p osition p er clo c k
cycle.
Left Shift :Q
i
?Q
i+1
, Righ t Shift :Q
i
?Q
i-1
• Dela y : Time tak en to shift data through an n -bit register.
t
dela y
=n·T
clo c k
where T
clo c k
is the clo c k p erio d.
• Applications : Data storage, data transfer, serial-to-parallel con v ersion, ring coun ter,
Johnson coun ter.
• Ring Coun ter : A shift register where the output of the last flip-flop is fed bac k to
the input.
Num b er of S tates =n
• Johnson Coun ter : A t wisted ring coun ter with in v erted feedbac k.
Num b er of States = 2n
Design P arameters
• Clo c k F requency : Determines the sp eed of coun ting/shifting.
f
clo c k
=
1
T
clo c k
• Propagation Dela y : T otal dela y in async hronous coun ters.
t
total
=n·t
p d
where t
p d
is the propagation dela y of one flip-flop.
• Setup and Hold Time : Ensure prop er flip-flop op eration.
t
setup
,t
hold
(sp ecified b y flip-flop datasheet)
Key Notes
• Use JK or T flip-flops for coun ters to simplify toggling logic.
• Sync hronous coun ters are faster than async hronous due to sim ultaneous clo c king.
• Chec k for un used states in non-binary coun ters (e.g., decade coun ter, Mo d-10).
• F or shift registers, ensure prop er initialization to a v oid indeterminate states.
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