IC Fabrication Technology Notes | EduRev

: IC Fabrication Technology Notes | EduRev

 Page 1


1
Lecture 33, Slide 1 EECS40, Fall 2003 Prof. King
Lecture #33
OUTLINE
• IC Fabrication Technology
–Doping
– Oxidation
– Thin-film deposition
– Lithography
–Etch
Reading (Rabaey et al.)
• Chapter 2.1-2.2
Lecture 33, Slide 2 EECS40, Fall 2003 Prof. King
Integrated Circuit Fabrication
Goal:
Mass fabrication (i.e. simultaneous fabrication) of many 
“chips”, each a circuit (e.g. a microprocessor or memory 
chip) containing millions or billions of transistors
Method:
Lay down thin films of semiconductors, metals and 
insulators and pattern each layer with a process much 
like printing (lithography).
Materials used in a basic CMOS integrated circuit:
• Si substrate – selectively doped in various regions
•SiO
2
insulator
• Polycrystalline silicon – used for the gate electrodes
• Metal contacts and wiring
Page 2


1
Lecture 33, Slide 1 EECS40, Fall 2003 Prof. King
Lecture #33
OUTLINE
• IC Fabrication Technology
–Doping
– Oxidation
– Thin-film deposition
– Lithography
–Etch
Reading (Rabaey et al.)
• Chapter 2.1-2.2
Lecture 33, Slide 2 EECS40, Fall 2003 Prof. King
Integrated Circuit Fabrication
Goal:
Mass fabrication (i.e. simultaneous fabrication) of many 
“chips”, each a circuit (e.g. a microprocessor or memory 
chip) containing millions or billions of transistors
Method:
Lay down thin films of semiconductors, metals and 
insulators and pattern each layer with a process much 
like printing (lithography).
Materials used in a basic CMOS integrated circuit:
• Si substrate – selectively doped in various regions
•SiO
2
insulator
• Polycrystalline silicon – used for the gate electrodes
• Metal contacts and wiring
2
Lecture 33, Slide 3 EECS40, Fall 2003 Prof. King
Si Substrates (Wafers)
Crystals are grown from a melt in boules (cylinders) with 
specified dopant concentrations.  They are ground 
perfectly round and oriented (a “flat” or “notch” is ground 
along the boule) and then sliced like baloney into wafers.  
The wafers are then polished. 
Typical wafer cost:  $50
Sizes:  150 mm, 200 mm, 300 mm diameter
300 mm
“notch” indicates
crystal orientation
Lecture 33, Slide 4 EECS40, Fall 2003 Prof. King
Suppose we have a wafer of Si which is p-type and we want to 
change the surface to n-type.  The way in which this is done is by 
ion implantation.  Dopant ions are shot out of an “ion gun” called 
an ion implanter, into the surface of the wafer.  
Typical implant energies are in the range 1-200 keV.   After the ion 
implantation, the wafers are heated to a high temperature (~1000
o
C).  
This “annealing” step heals the damage and causes the implanted 
dopant atoms to move into substitutional lattice sites.
Adding Dopants into Si
Eaton HE3
High-Energy 
Implanter,
showing the 
ion beam 
hitting the
end-station
x
SiO
2
Si
+ + + + + +
As
+
or P
+
or B
+ 
ions
x
SiO
2
Si
+ + + + + + + + + + + +
As
+
or P
+
or B
+ 
ions
Page 3


1
Lecture 33, Slide 1 EECS40, Fall 2003 Prof. King
Lecture #33
OUTLINE
• IC Fabrication Technology
–Doping
– Oxidation
– Thin-film deposition
– Lithography
–Etch
Reading (Rabaey et al.)
• Chapter 2.1-2.2
Lecture 33, Slide 2 EECS40, Fall 2003 Prof. King
Integrated Circuit Fabrication
Goal:
Mass fabrication (i.e. simultaneous fabrication) of many 
“chips”, each a circuit (e.g. a microprocessor or memory 
chip) containing millions or billions of transistors
Method:
Lay down thin films of semiconductors, metals and 
insulators and pattern each layer with a process much 
like printing (lithography).
Materials used in a basic CMOS integrated circuit:
• Si substrate – selectively doped in various regions
•SiO
2
insulator
• Polycrystalline silicon – used for the gate electrodes
• Metal contacts and wiring
2
Lecture 33, Slide 3 EECS40, Fall 2003 Prof. King
Si Substrates (Wafers)
Crystals are grown from a melt in boules (cylinders) with 
specified dopant concentrations.  They are ground 
perfectly round and oriented (a “flat” or “notch” is ground 
along the boule) and then sliced like baloney into wafers.  
The wafers are then polished. 
Typical wafer cost:  $50
Sizes:  150 mm, 200 mm, 300 mm diameter
300 mm
“notch” indicates
crystal orientation
Lecture 33, Slide 4 EECS40, Fall 2003 Prof. King
Suppose we have a wafer of Si which is p-type and we want to 
change the surface to n-type.  The way in which this is done is by 
ion implantation.  Dopant ions are shot out of an “ion gun” called 
an ion implanter, into the surface of the wafer.  
Typical implant energies are in the range 1-200 keV.   After the ion 
implantation, the wafers are heated to a high temperature (~1000
o
C).  
This “annealing” step heals the damage and causes the implanted 
dopant atoms to move into substitutional lattice sites.
Adding Dopants into Si
Eaton HE3
High-Energy 
Implanter,
showing the 
ion beam 
hitting the
end-station
x
SiO
2
Si
+ + + + + +
As
+
or P
+
or B
+ 
ions
x
SiO
2
Si
+ + + + + + + + + + + +
As
+
or P
+
or B
+ 
ions
3
Lecture 33, Slide 5 EECS40, Fall 2003 Prof. King
e.g. AsH
3 
gaseous source
As
+
, AsH
+
, H
+
, AsH
2
+
Ion
source
translational
motion
As
+
accelerator
Energy: 1 to 200 keV
Dose: 10
11 
to10
16
/cm
2
Inaccuracy of dose: <0.5%
Nonuniformity: <1%
Throughput: ~60 wafers/hr
ion beam
wafer
spinning wafer
holder
Ion Implanter
F = q( v × B )
•
analyzer magnet
resolving aperture
Lecture 33, Slide 6 EECS40, Fall 2003 Prof. King
• The implanted depth-profile of dopant atoms is peaked.
• In order to achieve a more uniform dopant profile, high-
temperature annealing is used to diffuse the dopants
• Dopants can also be directly introduced into the surface of 
a wafer by diffusion (rather than by ion implantation) from 
a dopant-containing ambient or doped solid source
Dopant Diffusion
dopant atom
concentration
(logarithmic
scale)
as-implanted profile
depth, x
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