Input Output Organization | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE) PDF Download

Modes of transfer

• Data Transfer between the central computer and I/O devices may be handled in a variety of modes.
• Some modes use CPU as an intermediate path, others transfer the data directly to and from the memory unit.
• Data transfer to and from peripherals may be handled in one of three possible modes.
  • Programmed I/O
  • Interrupt Driven I/O
  • Direct Memory Access (DMA)

Programmed I/O 

• Programmed I/O operations are the result of I/O instructions written in the computer program.
• In programmed I/O, each data transfer in initiated by the instructions in the CPU and hence the CPU is in the continuous monitoring of the interface. ·
• Input instruction is used to transfer data from I/O device to CPU, store instruction is used to transfer data from CPU to memory and output instruction is used to transfer data from CPU to I/O device.
• This technique is generally used in very slow speed computer and is not a efficient method if the speed of the CPU and I/O is different.

• I/O device places the data on the I/O bus and enables its data valid signal
• The interface accepts the data in the data register and sets the F bit of status register and also enables the data accepted signal.
• Data valid line is disables by I/O device.
• CPU is in a continuous monitoring of the interface in which it checks the F bit of the status register.
  • If it is set i.e. 1, then the CPU reads the data from data register and sets F bit to zero
  • If it is reset i.e. 0, then the CPU remains monitoring the interface.
• Interface disables the data accepted signal and the system goes to initial state where next item of data is placed on the data bus.

Characteristics: 

• Continuous CPU involvement
• CPU slowed down to I/O speed
• Simple
• Least hardware

Polling, or polled operation, in computer science, refers to actively sampling the status of an external device by a client program as a synchronous activity. Polling is most often used in terms of input/output (I/O), and is also referred to as polled I/O or software driven I/O. 

Interrupt-driven I/O

• Polling takes valuable CPU time
• Open communication only when some data has to be passed -> Interrupt.
• I/O interface, instead of the CPU, monitors the I/O device
• When the interface determines that the I/O device is ready for data transfer, it generates an Interrupt Request to the CPU
• Upon detecting an interrupt, CPU stops momentarily the task it is doing, branches to the service routine to process the data transfer, and then returns to the task it was performing

The problem with programmed I/O is that the processor has to wait a long time for the I/O module of concern to be ready for either reception or transmission of data. The processor, while waiting, must repeatedly interrogate the status of the I/O module. As a result, the level of the performance of the entire system is severely degraded. An alternative is for the processor to issue an I/O command to a module and then go on to do some other useful work. The I/O module will then interrupt the processor to request service when it is ready to exchange data with processor. The processor then executes the data transfer, and then resumes its former processing. The interrupt can be initiated either by software or by hardware.

Interrupt Driven I/O basic operation

• CPU issues read command
• I/O module gets data from peripheral whilst CPU does other work
• I/O module interrupts CPU
• CPU requests data
• I/O module transfers data Interrupt

Processing from CPU viewpoint 

• Issue read command
• Do other work
• Check for interrupt at end of each instruction cycle
• If interrupted:-
  • Save context (registers)
  • Process interrupt
  • Fetch data & store

Priority Interrupt 

• Determines which interrupt is to be served first when two or more requests are made simultaneously
• Also determines which interrupts are permitted to interrupt the computer while another is being serviced
• Higher priority interrupts can make requests while servicing a lower priority interrupt 

Priority Interrupt by Software (Polling)

• Priority is established by the order of polling the devices (interrupt sources), that is identify the highest-priority source by software means
• One common branch address is used for all interrupts
• Program polls the interrupt sources in sequence
• The highest-priority source is tested first
• Flexible since it is established by software
• Low cost since it needs a very little hardware
• Very slow 

Priority Interrupt by Hardware 

• Require a priority interrupt manager which accepts all the interrupt requests to determine the highest priority request
• Fast since identification of the highest priority interrupt request is identified by the hardware
• Fast since each interrupt source has its own interrupt vector to access directly to its own service routine

1. Daisy Chain Priority (Serial)

• Interrupt Request from any device
• CPU responds by INTACK
• Any device receives signal(INTACK) at PI puts the VAD on the bus
• Among interrupt requesting devices the only device which is physically closest to CPU gets INTACK and it blocks INTACK to propagate to the next device

2. Parallel Priority

• IEN: Set or Clear by instructions ION or IOF
• IST: Represents an unmasked interrupt has occurred. INTACK enables tristate Bus Buffer to load VAD generated by the Priority Logic
• Interrupt Register:
  • Each bit is associated with an Interrupt Request from different Interrupt Source - different priority level
  • Each bit can be cleared by a program instruction
• Mask Register:       
  • Mask Register is associated with Interrupt Register
  • Each bit can be set or cleared by an Instruction

Priority Encoder

• Determines the highest priority interrupt when more than one interrupts take place

• CPU checks IEN and IST
• If IEN and IST = 1, CPU -> Interrupt Cycle
  • SP  SP – 1; Decrement stack pointer
  • M[SP]  PC; Push PC into stack
  • INTACK  1; Enable interrupt acknowledge
  • PC  VAD; Transfer vector address to PC
  • IEN  0; Disable further interrupts
  • Go To Fetch to execute the first instruction in the interrupt service routine

Direct Memory access

• Large blocks of data transferred at a high speed to or from high speed devices, magnetic drums, disks, tapes, etc.
• DMA controller Interface that provides I/O transfer of data directly to and from the memory and the I/O device
• CPU initializes the DMA controller by sending a memory address and the number of words to be transferred
• Actual transfer of data is done directly between the device and memory through DMA controller -> Freeing CPU for other tasks

The transfer of data between the peripheral and memory without the interaction of CPU and letting the peripheral device manage the memory bus directly is termed as Direct Memory Access (DMA). 

The two control signals Bus Request and Bus Grant are used to fascinate the DMA transfer. The bus request input is used by the DMA controller to request the CPU for the control of the buses. When BR signal is high, the CPU terminates the execution of the current instructions and then places the address, data, read and write lines to the high impedance state and sends the bus grant signal. The DMA controller now takes the control of the buses and transfers the data directly between memory and I/O without processor interaction. When the transfer is completed, the bus request signal is made low by DMA. In response to which CPU disables the bus grant and again CPU takes the control of address, data, read and write lines.

The transfer of data between the memory and I/O of course facilitates in two ways which are DMA Burst and Cycle Stealing.

DMA Burst:
The block of data consisting a number of memory words is transferred at a time.Cycle Stealing: DMA transfers one data word at a time after which it must return control of the buses to the CPU.

• CPU is usually much faster than I/O (DMA), thus CPU uses the most of the memory cycles
• DMA Controller steals the memory cycles from CPU
• For those stolen cycles, CPU remains idle
• For those slow CPU, DMA Controller may steal most of the memory cycles which may cause CPU remain idle long time     

DMA Controller
The DMA controller communicates with the CPU through the data bus and control lines. DMA select signal is used for selecting the controller, the register select is for selecting the register. When the bus grant signal is zero, the CPU communicates through the data bus to read or write into the DMA register. When bus grant is one, the DMA controller takes the control of buses and transfers the data between the memory and I/O.

The address register specifies the desired location of the memory which is incremented after each word is transferred to the memory. The word count register holds the number of words to be transferred which is decremented after each transfer until it is zero. When it is zero, it indicates the end of transfer. After which the bus grant signal from CPU is made low and CPU returns to its normal operation. The control register specifies the mode of transfer which is Read or Write.

• DMA sends the bus request signal to CPU in response to which CPU disables its current instructions and initialize the DMA by sending the following information.
  • The starting address of the memory block where the data are available (for read) and where data to be stored (for write)
  • The word count which is the number of words in the memory block
  • Control to specify the mode of transfer
  • Sends a bust grant as 1 so that DMA controller can take the control of the buses
  • DMA sends the DMA acknowledge signal in response to which peripheral device puts the words in the data bus (for write) or receives a word from the data bus (for read)

DMA Operation 

• CPU tells DMA controller:-
  • Read/Write
  • Device address
  • Starting address of memory block for data
  • Amount of data to be transferred
• CPU carries on with other work
• DMA controller deals with transfer
• DMA controller sends interrupt when finished

I/O Processors 

• Processor with direct memory access capability that communicates with I/O devices
• Channel accesses memory by cycle stealing
• Channel can execute a Channel Program
• Stored in the main memory
• Consists of Channel Command Word(CCW)
• Each CCW specifies the parameters needed by the channel to control the I/O devices and perform data transfer operations
• CPU initiates the channel by executing a channel I/O class instruction and once initiated, channel operates independently of the CPU

A computer may incorporate one or more external processors and assign them the task of communicating directly with the I/O devices so that no each interface need to communicate with the CPU. An I/O processor (IOP) is a processor with direct memory access capability that communicates with I/O devices. IOP instructions are specifically designed to facilitate I/O transfer. The IOP can perform other processing tasks such as arithmetic logic, branching and code translation.

The memory unit occupies a central position and can communicate with each processor by means of direct memory access. The CPU is responsible for processing data needed in the solution of computational tasks. The IOP provides a path for transferring data between various peripheral devices and memory unit.

In most computer systems, the CPU is the master while the IOP is a slave processor. The CPU initiates the IOP and after which the IOP operates independent of CPU and transfer data between the peripheral and memory. For example, the IOP receives 5 bytes from an input device at the device rate and bit capacity. After which the IOP packs them into one block of 40 bits and transfer them to memory. Similarly the O/P word transfer from memory to IOP is directed from the IOP to the O/P device at the device rate and bit capacity.

CPU – IOP Communication
The memory unit acts as a message center where each processor leaves information for the other. The operation of typical IOP is appreciated with the example by which the CPU and IOP communication

• The CPU sends an instruction to test the IOP path.
• The IOP responds by inserting a status word in memory for the CPU to check.
• The bits of the status word indicate the condition of the IOP and I/O device, such as IOP overload condition, device busy with another transfer or device ready for I/O transfer.
• The CPU refers to the status word in in memory to decide what to do next.
• If all right up to this, the CPU sends the instruction to start I/O transfer.
• The CPU now continues with another program while IOP is busy with I/O program.
• When IOP terminates the execution, it sends an interrupt request to CPU. · CPU responds by issuing an instruction to read the status from the IOP.
• IOP responds by placing the contents to its status report into specified memory location.
• Status word indicates whether the transfer has been completed or with error.