Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

VLSI System Design

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Electrical Engineering (EE) : Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

The document Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course VLSI System Design.
All you need of Electrical Engineering (EE) at this link: Electrical Engineering (EE)

  

Objectives

In this course you will learn the following

  • Background
  • λ-based Design Rules


14.1 Background

As we studied in the last lecture, Layout rules are used to prepare the photo mask used in the fabrication of integrated circuits. The rules provide the necessary communication link between the circuit designer and process engineer. Design rules represent the best possible compromise between performance and yield.

The design rules primarily address two issues -

1. The geometrical reproductions of features that can be reproduced by mask making and lithographical processes. 

2. Interaction between different layers


Design rules can be specified by different approaches

1. λ-based design rules
2. µ-based design rules

As λ-based layout design rules were originally devised to simplify the industry- standard µ-based design rules and to allow scaling capability for various processes. It must be emphasized, however, that most of the submicron CMOS process design rules do not lend themselves to straightforward linear scaling. The use of λ-based design rules must therefore be handled with caution in sub-micron geometries.

In further sections of this lecture, we will present a detailed study about λ-based design rules.

 

14.2 λ-based Design Rules

Features of λ-based Design Rules : λ-based Design Rules have the following features-

 

  • λ is the size of a minimum feature
  • All the dimensions are specified in integer multiple of λ.
  • Specifying λ particularizes the scalable rules.
  • Parasitic are generally not specified in λ units
  • These rules specify geometry of masks, which will provide reasonable yields


Guidelines for using λ-based Design Rules:

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

As, Minimum line width of poly is  & Minimum line width of diffusion is 

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

As Minimum distance between two diffusion layers 

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

As It is necessary for the poly to completely cross active, other wise the transistor that has been created crossing of diffusion and poly, will be shorted by diffused path of source and drain.

λ-based Design Rules

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

Contact cut on metal

Contact window will be of  by  that is minimum feature size while metal deposition is of  by  for reliable contacts.

 

In Metal

Two metal wires have  distance between them to overcome capacitance coupling and high frequency coupling. Metal wires width can be as large as possible to decrease resistance.

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev


Buttering contact

Buttering contact is used to make poly and silicon contact.
Window's original width is , but on overlapping width is .
So actual contact area is  by .

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

The distance between two wells depends on the well potentials as shown above. The reason for 8l is that if both wells are at same high potential then the depletion region between them may touch each other causing punch-through. The reason for 6l is that if both wells are at different potentials then depletion region of one well will be smaller, so both depletion region will not touch each other so 6l will be good enough.

Layout Design Rules (Part - 2) Electrical Engineering (EE) Notes | EduRev

The active region has length 10λ which is distributed over the followings-

  • for source diffusion
  •   for drain diffusion
  •  2λ for channel length
  •  2λ for source side encroachment
  •  2λ for drain side encroachment 
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