MOS Transistors - IV - VLSI Circuits & Systems Video Lecture - Computer Science Engineering (CSE) | Best Video for Computer Science Engineering (CSE)

hello and welcome to today's lecture on
MOS transistors this is the last lecture
on this topic today I shall discuss
about MOS transistor as a switch in the
last couple of lectures I have discussed
how MOS transistor can be fabricated and
then basic structure of a MOS transistor
then I have explained the operation of a
MOS transistor with the help of a very
simple model known as fluid model and in
my last lecture I have discussed the
electrical characteristics of the MOS
transistor and I have derived expression
for the drain current and we have seen
what are the various parameters on which
the drain current depends today I shall
discuss one very important application
of MOS transistor that is transistor as
a switch and here is the agenda of
today's lecture I shall give a brief
introduction about days and then I shall
start with MOS transistor as a switch
why do you require a MOS transistor as a
switch then P Mo's transistor as a
switch transmission gate then
transmission gate driving a large
capacitor capacitive load then I shall
consider transmission gate driving a
small capacitive load then I shall
summarize what I have discussed
first I shall discuss what is a switch
you may have hard off switch
rather everyday you are using switch in
your day-to-day life what do you really
mean by switch you see as you get off
you have to turn on the light and you
use a switch electrically it can be
represented by this so it has got two
contacts and you are taking connections
then these connections can be connected
to a say AC supply and maybe it is in
series with a lamp so this type of
switch is known as toggle switch that
means if you push it it will be closed
and whenever you push it on the other
side it will be open that means it has
got to straight close and open or you
can say closes you can write it is as on
and off you can also write this way so
this kind of switch which is known as
mechanical switch you are using in your
everyday day-to-day life to turn on
lights fans various types of electrical
and electronic devices and as you as you
can see it has got two states there is
another type of switch which is known as
electromechanical this is you can also
call it a relay is being used in many
electronic circuits what is a relay it
has got a magnet electromagnet and
switches there is one middle point you
can see there are three contacts I have
shown and if you pass current obviously
have to pass DC current because it is a
relay and whenever you pass current
through it this particular middle
contactor is attracted to this that
means these two lines will make contact
and whenever no current is passed
through it so that means you have got
you can say another switch that can be a
in fact electronic switch or some
mechanic is some others type of switch
but the current passing through is not
very high but here the current that can
be passing through it can be very large
so this is a relay as you can see it has
again got three contacts middle one then
at this side that means whenever this
electromagnet magnet is energized these
two lines say s 1 and s 2 makes contact
and whenever this is not energized then
s 1 and s 3 makes contact here also it
has got to state again on and off if
you are using an a these two can be used
for connecting some electronic circuits
like say Bazaar or a tiresome oven or
anything of that kind which can be
controlled electronically so this type
of switch is very popular now today
obviously we shall be discussing about
the use of another switch that is
transistor as a switch that two MOS
transistor now whenever we go to use the
MOS transistor as a switch before we do
discuss that let us consider another
very important aspect that is
characteristics of an ideal switch so
whenever we say switch it has some
characteristic
ideal non-ideal what do you really mean
by an ideal switch say whenever we close
it then current passes through it and
whatever is the voltage say this is your
V that is a that is applied across this
lamp you can say now whenever we call
consider a switch is ideal when the on
resistance is zero on resistance is zero
that means whenever it is put on there
is no resistance it does not offer any
resistance so the fault of whatever
voltage you apply that is that is
applied across the lamp there is no
voltage drop across the switch so an
ideal switch does not degrade the signal
that is the characteristic on the other
hand if it is similarly whenever it is
off then resistance
is very high or I mean ideally infinite
but even when if it is very high it will
serve the purpose that means of
resistance would be infinite so whenever
these two characteristics are satisfied
we call it an ideal switch and obviously
in such a situation whatever signal is
connected through the switch will not be
degraded or distorted the signal will
reach the load in this case lamp is the
load without any degradation or
distortion so this is how we define an
ideal switch and obviously whenever it
is non-ideal on resistance in real in
the in reality anything will have some
finite resistance that means whenever it
is on it will have some finite
resistance and whenever it is off that
resistance may be very high but
obviously it will not be infinite so
that will be the situation of a
practical switch obviously we shall see
how the Mo's transistor behaves in terms
of this ideal characteristics okay we
have already discussed the we can say
MOS transistor characteristic we have
already discussed we know that it is a
variation of drain current as you change
the drain voltage and that that is for
different gate voltages so these are the
different gate voltages and as we know
there are three modes number one is your
number one is your cutoff then the this
line represents that cutoff region when
there is no current passing through it
then we have seen there is another
region that is your linear
and finally saturation so this is your
saturation region we have already
discussed that so we have to understand
whenever we try to use MOS transistor as
a switch where it will operate in which
mode it will operate at which point it
will be operating when it is off or on
obviously when it is off it will be in
the cutoff region that means MOS
transistor is off it will be cut off and
whenever it is on it may be in linear or
in saturation on which factor it depends
that means whenever the Boston stir is
on it will be either in one of the two
states linear or saturation on which
factor it will depend it will depend on
the voltage across the device that means
radius as you have seen if VDS the
voltage across it is less than vgs minus
VT then it will be in the linear mode
linear or non saturated mode on the
other hand it will be in the saturated
saturation mode or saturated mode
whenever VDS is greater then vgs minus
VT so this line this is the line this is
VDS is equal to vgs minus VT demarcates
the operation between linear region and
saturation region and obviously whenever
you are using it as a switch you may not
have control about the voltage across it
or in other words it may vary so it may
operate the switch may be closed by
applying a suitable gate voltage that
means whenever it is
it will be made on by applying again
voltage which is greater than VT
threshold voltage and op means the gate
voltage is that means vgs is less than
VT and on means vgs is greater than VT
but the operation will depend on the
value of the VDS drain to source voltage
and as we shall see later whenever the
transistor is on it may 8th operation
will vary from one mode to another mode
it will make a switch it may go from
linear to saturation or saturation to
linear and so on
it will depend on the application then
as you already know for most transistor
resistance is - the gate voltage is less
than the threshold voltage as I have
already told so this is in this mode it
n is DD used as a op State of a switch
and for a MOS transistor resistance is
low when the gate voltage is more than
the threshold voltage which I have
already mentioned that means whenever it
is on now let us consider the use of n
Mo's transistor as a switch so n Mo's
transistor can be represented by this
here one point you must notice you are
not applying input to the gate gate is
used to control the operation of the
switch you are applying input to one of
the two terminals source or drain and in
case of a MOS transistor one very
interesting factor is the transistor I
mean the source and drain are perfectly
symmetrical that means any one of the
two terminals can be used as source the
other one can be used as drain
unlike you know bipolar transistors in
case of bipolar transistors you cannot
really interchange you know that that
emitter and collector that's an emitter
collector and emitter cannot be
interchange their operation will be
different but in case of a MOS
transistor we have already seen this
structure and from the structural
viewpoint we have seen the physical
structure is identical and as a
consequence later on we shall see same
terminal samjha sometime sometimes it is
operating as a source at other point of
time it is operating as a drain as we go
for discussing the operation of a MOS
transistor so whenever here you are
applying let's assume whenever you apply
zero then whenever this is your vgs that
means first let us consider when vgs is
equal to zero gate to source voltage is
zero obviously here we assumed here this
is the source and this is the drain and
he is that gate vgs is zero in this
particular condition the transistor is
off that we have already same is off but
whenever this transistor is off what
will be the output say suppose you have
applied a zero volt here can will you
get zero voltage at the output or
suppose you apply say +5 volt which we
consider to be 1 will you get a +5 volt
there is a question mark why I have put
the question mark the reason for that is
you know the output is essentially comes
can be considered that there is a
capacitor connected to it
why we this this MOS transistor may be
connected to other parts of the circuit
say suppose it has been connected to an
inverter and as we know this inverter
this
they are connected to the base and they
were they are having capacitance so we
can say here there will be a load
capacitance CL and obviously CL will
hold the charge and the output will be
dependent on what was whatever was the
input before it was turned off that
means it is acting as a kind of memory
output does not fully depend on the
present input just prior to closing of
putting the switch off whatever was the
input that output will be available as
you turn it off
and in fact this property can be used to
realize memory devices using MOS
transistors in fact the dynamic Ram that
is being that is that is realized is
they are precisely it is used in this
way that means the intrinsic capacitor
is used to hold the information so that
is the reason he why here whenever vgs
is equal to zero the transistor is off
but output is not defined not defined
means it depends on the previous state
so since its acts as a memory now let us
consider the case whenever vgs is equal
to VDD that means you have you have
applied instead of zero you have applied
say plus 5 volt VDD supply voltage in
this case what will happen in this case
the transistor is on transistor is on
now transistor is on
but what voltage you will get at the
output will it will you get zero or you
will get
more than 0 or less than zero depending
on the previous state you see you are
applying +5 volt here and this is zero
and obviously this transistor will
always remain on I mean
irrespective of the output so this zero
I mean if this capacitor was let's
assume earlier there was a voltage plus
5 volt here and it will discharge to
zero eventually it may take some time
because of the finite resistance of the
transistor but in the steady state
output will become zero that means if V
in V in is 0 then V out V out is also
zero volt in the steady state that means
the as you can see the low level voltage
since we are concerned about you know
digital circuits our input is high or
low zero or 5 volt so this zero level
low level is passing to the output
without any Distortion whenever the
input voltage is say 5 volt what about V
out yes so output you see this the here
5 volt here 5 volt here you can see the
role of this these two terminals has
reversed it is no longer source you can
consider it as drain and this as source
so since this is as this is 5 volt and
initially maybe this is 0 so this
transistor is on but as this capacitor
output capacitor CA charges gradually it
will reach the point where the voltage
will be equal to VDD minus VT which is a
threshold voltage of this MOS transistor
at that point distance tur will turn off
so that means output cannot charge
beyond VDD minus VT or say VT n to
signify in MOS transistor so we can see
here the as the input input voltage is
VDD you are not getting full output
voltage it is getting degraded and
output will be VDD minus VT n that means
it will be less by the threshold voltage
of the mass transfer because at that
point of time the transistor is turning
off so here it is plus 5 volt there it
is blowing and then in the gate it is
plus 5 volt and here at this point it is
VDD minus VT so if it rises further the
transistor transform so you can see in
case of a n MOS transistor you are not
getting the full output it is getting
degraded okay what about P MOS say let
us now consider the P Mo's transistor
emos
in case of a Pima strange step let me
draw the diagram for Effie Mo's
transistor this is a Primus transistor
now in this case whenever you apply zero
volt then what will be the situation of
this then the transistor is on that
means whenever input I mean gate vgs is
equal to zero volt then the transistor
is on the transistor is on on the other
hand whenever you apply vgs is equal to
plus 5 volt then the transistor is off
irrespective of the inputs that you
apply transistor is off that means
whenever the it is plus 5 volt then the
10 stare is off so again the transistor
behaves like a you know kind of memory
we have already seen the output cannot
be fully defined it does not fully
depend on the present input it depends
on the past input so at the point of
time when it was switched from 0 to 5
volt at that point of time whatever was
the input that that output that input
will reach the output and it will be
retained by the capacitance that is
present here on the other hand whenever
vgs is equal to 0 the transistor is on
let us say the operation of the most
transistor when the transistor is on
that means whenever V in is equal to 0
volt vgs is equal to zero volt at that
time what is V output what is V output
we have assumed that vgs is equal to
zero volt what will be the output you
see here zero volt here it is zero volt
so there is no difference and initially
let us assume this was classified so
this source is gate is more negative
with respect to this source so the
transistor is on but how long it will
remain on as the capacitor charges it
will turn off whenever it will reach VDD
minus VT n VT P absolute value of the
threshold voltage of the Moss transistor
and at that point the transistor will
turn off and so you can see here here
the zero level is not reaching the
output properly that the low level
voltage is getting degraded what about V
in is equal to plus 5 volt so here
instead of zero we apply +5 volt what
will be the output let us assume
initially it was plus 5 volt you can say
in this particular case this is this is
now acting as a source this is acting as
a drain and this transistor is always on
because gate is more negative with
respect to the source plus 5 volt so the
transistor is always on that means the V
output will be equal to plus 5 volt that
means the high level voltage is reaching
without any degradation so the
characteristic is exactly opposite to
that of n MOS transistor we have seen in
case of n MOS transistor the low level
signal was passing without any
degradation high level was degraded in
case of P Mo's just the opposite the
high level is reaching without
degradation low level is getting
degraded okay
now can we now get best of both the
words we have seen that the in most and
neither
n MOS transistor not Pima Sten Sture
behaves like a ideal switch either low
level is degraded or high level is
degraded depending only depending on the
type of transistor you are using is
there any way by which we can get best
of both the words that means the good
features of both the transistors we try
to achieve how can we do that we can do
that by combining two transistors in
parallel so what we can do we can have a
PMO's transistor in parallel with a n
MOS transistor so this is n Mo's
transistor then this is a famous
transistor and this is your V in and
this is your V out obviously you you can
turn them off by applying say +5 volt
and zero so in that case it will be s it
will be both the transistors are off so
it will behave our the output will
behave like your NMOS or PMO's
transistor that means in this particular
case output is dependent on the previous
value so as you can see we have to apply
complementary complementary output
impure inputs to the gate gates of these
two transistors that means you have to
make them simultaneously on or
simultaneously off so in this particular
case they are off so here the output
voltage will be dependent on the
previous state now to make the switch on
let us apply five volt here and zero
volt here that means V G s n is equal to
plus 5 volt n MOS transistor we are
applying +5 volt and V G SP we are
applying zero volt that means the switch
is on in this case if you apply V in is
equal to zero volt what will be the
output what will be the output voltage
you can see you have now two transistors
in parallel okay
the the PMO's transistor in this
particular case will not pass the zero
voltage but it will pass through the N
Mo's transistor that means it is zero
volt so it is always on so output will
be output will be zero that means a low
level signal will pass through the N
Mo's transistor without any degradation
similarly if you apply VDD or +5 volt
the output will be again plus 5 volt a
high level signal will pass through the
PMO's transistor without any degradation
so you can see now we are getting a kind
of ideal switch in terms of you know it
may not be perfectly ideal but ideal in
terms of that you are getting the low
level and high level are passing without
any degradation so and this particular
device is known as transmission gate
which is realized by combining two
transistors in parallel in Mo's and P
Mo's transistors and applying
complementary output complementary
inputs to the gates and by that you can
turn the switch on or off okay now so
far we have considered only the use of P
Mo's and I made different types of
switches to realize to check whether the
logic levels are passing to through it
out properly or not
now we shall study dynamic behavior of
the switch and we shall see whether how
the current is here
by these two transistors do this here
equally or you know there are currents
hearing changes as the input and output
changes so we shall study kind of
dynamic behavior and to do that we shall
consider this each case where the
transmission gate is driving a large
capacitive load that means you have got
a transmission switch I mean
transmission switch P Mo's and n Mo's in
parallel and let's assume let us not
bother about the off condition let's
assume both the 10 zips sorry I put the
opposite way that means in this
particular case the output will be it
will be it will be off let us consider
the case where we are considering the
both the transistors are on so here you
are applying 0 volt and here plus 5 volt
and the transistor is on in this
particular case what we have done we
have assumed that here you have got a
large capacitive load by largely mean
this capacitance value is relatively
high compared to the intrinsic
capacitances of the devices which is of
the order of femto farad maybe this is
of the order of Pico farad not femto
farad then we consider it large Pico
farad may not be a very large
capacitance but when we consider in
terms of MOS transistors capacitances
then it is large because the intrinsic
capacitances like gate capacitance
source capacitance these are of the
order of femto farad so these are in the
range of let
it is several picofarad now what we are
doing we are changing the you are
applying a input
and suddenly changing it from VDD to 0
to VDD 0 to VDD we are changing it from
0 to VDD input is instantly
instantaneously changed from 0 to VDD so
you are using it you are applying a step
input what will happen at the output so
since this as we know this time the both
the transistors are on so obviously this
assuming that initially this was 0 volt
it will start charging so we can say
that the output the capacitance so this
is V n VN had changed from say let us
assume this is this is the time this is
T is equal to 0 at this point it had
changed from 0 to 1 what about V output
what will happen obviously at this point
the output this is your V out and in
this axis it is T so initially the
voltage was 0 so it will charge it will
charge the capacitor will charge and
output will gradually build up and it
will go from 0 to VDD eventually so at
the output at the output goes from 0
volt to VDD during this period of time
obviously this time will be dependent on
the own resistances of these transistors
which are not 0 if the own resistances
were at 0 it would have charged instant
instantaneously but this will not happen
because the own resistances are not
really 0 they have finite on resistances
and the capacitor will gradually charge
from 0 to VDD and during this period we
shall see the condition of these
transistors how they change with time
from this zero to say t1 this is the
time during which they ought to be
charging from 0 to VDD okay so initially
what will be the condition of these two
states we can divide the operation in
three regions region 1 region 2 and
region 3 how we shall define the three
regions say initially what will be their
States you can see here this here it is
VDD and here it is 0 fault so how do be
the condition of these two transistors
in which state they will be fatigue the
mode will live in upstate will live in
linear state or will live in saturation
state you can see here since this is
zero here initially this is this is VDD
at time T and output a and this V out is
zero and input is VD D so in this
particular case this both the
transistors will be on it will be on Y
because this is 0 and this is VDD so
this is acting as a source this is
acting at a source and this is acting as
a drain for the PMO's transistor so this
transistor will be on and since large
voltage is applied across it the
transistor will be in the saturation
mode similarly for this transistor this
is this output is zero so this can be
considered as source this can be
considered as drain and this is gate
so again a distance that will be on and
since the voltage difference is VDD
again the ten steps will be this
transistor will be in saturation that
means we can say both the transistors
are in saturation both P Mo's and n Mo's
transistors are in saturation when when
their state will change when the
condition of the transistors will change
you can see so far as the P Mo's
transistor is considered zero volt and
VDD fixed so this transistor will always
remain on however it may switch from
saturation to linear a a point will
reach when this is equal to VT P
absolute value of VT P that means the
voltage is charging and ETH reaches the
absolute value of VT P at that point of
time the P Mo's transistor will switch
from saturation to linear saturation to
linear mode that means in this case P
MOS in linear what about n MOS in most
case we can see the voltage here is VDD
this voltage is VDD in this particular
case what is happening the the voltage
the transistor is in saturation but what
will happen the the Enma it will remain
in saturation because the gate voltage
and the gate voltage and drain voltage
both are changing we can say you can see
this is this is remaining same then then
to source this voltage is changing and
gate to source both this is also
changing because
is rising so n moss will remain in
saturation
and what about region 3 region 3 will
occur when the voltage is at this point
which is equal to VDD minus VT n
whenever it reaches this point then what
will happen this transistor will turn
off because here it is VDD minus VT this
is VDD and this is VDD so this
transistor the source student voltage
will become less than VT at beyond this
point so this n MOS transistor will turn
off that means P Mo's we will continue
continue to function in linear mode and
n MOS will turn off so you can see as
the capacitor charges the we have
assumed that it is linearly charging but
we shall see whether it is linearly
charged or not because we can we can see
here the transistor conditions are
changing in the region 1 both are in
saturation obviously the current drive
will be high whenever this is the case
then as it goes to the z n2 p MOS is
going to linear mode and n MOS remains
in saturation current drive will reduce
and when in the region 3 p MOS in linear
mode and n MOS is off so current type
will will be less that means the current
here we have assumed recharging at
constant current but that is not true
that means the current is changing as
the capacitor is gradually charging so
it will be maximum in the initial part
that this first part 0 to absolute value
of VT P and in this mode like it will be
moderate and it will be low okay so but
we have identified three regions of
operation whenever you drive a large cap
stip load and how the current changes
now we shall discuss how the current
changes we can we can derive the
expression for current we are we have
all in the last lecture we have
discussed the linearly saturation
current non saturation current I mean
when the transistor is non saturated
mode what is the expression for current
and in the saturation mode what is the
expression for a pop current that we
have expressed in terms of the drain
voltage gate to source voltage and we
know the drain voltage and gate to
source voltage is various voltages are
known to us because you can see here the
output valve voltage is changing so for
this particular transistor the gate to
source voltage is changing because it is
equal to VDD minus V output on the other
hand in this case the gate voltage is
remaining same however drain to source
voltage is changing and accordingly you
can derive expression for current in
region one in region two and in Region
three because we know the expression for
current for linear and such linear mode
and saturation modes
okay so let us consider that we redraw
it so this is the time and three
different regions we have already
divided now consider the current ID I
so let us we have already divided into
three parts starting from here so in the
first part the the what happens to the
this particular PMO's transistor the
most transistors is remaining in
saturation in in region one and region
two in Region three it is going to
linear mode so the characteristic for
the PMO's transistor will be somewhat
like this this is your that means in
this in these two regions region one and
region two this is the I D s P the P
Mo's transistor current is depicted by
this it is in saturation mode in region
one in region two in the region three it
is in the linear mode as you can see
what about the N Mo's transistor for n
Mo's transistor we have seen it is in it
is in saturation in region one and
region two but in Region three it is
turning off but although this transistor
is in saturation but is gate to source
voltage is changing gate to source
voltage and the when the transistor is
in saturation and gate to source voltage
changes what happens we have seen that
the drain current drain current changes
following square law it's not linear at
the gate voltage is reduced they you
know that I have although I have drawn
it equally spaced but you know that we
have seen that expression is dependent
on vgs minus VT whole square so it will
reduce following a square law so that
means here what will happen the assuming
that initially it is current is same so
it will be somewhat like this
it will reduce it will reduce not
linearly but it will reduce
quadratically so this is your I D s n so
I have not really drawn and I mean
written the expression for currents but
I have simply drawn the waveforms
current expression you can write because
you know the gate voltage you know the
drain voltage and you can write the
expression for drain current for P Mo's
transistor and n MOS transistor now the
current that will be charging the
capacitor the capacitor is connected
here because the the capacitor that will
be it will be charging obviously this
one will be having will the the sum of
these currents will flow through the
capacitor so what will be the value it
will be double here so that means it
will it will be somewhat like this if we
sum up these two this part is constant
so it will be nature for this part
nature will be somewhat similar to this
because you have summing up then it will
be like this so you can see it is not
really constant so that means over this
period as I mentioned earlier current
will be maximum in this range but it is
reducing then it will it is it will
further reduce then it will become the
linear mode current of the PMO's
transistor so this will be the current
that will be passing through the device
okay so this is the current explai
current that will be charging the
capacitor and it will charge to 0 to VDD
okay what about the yeah here the same
thing is no region 1 region 2 and region
3 I have already explained and the type
of card that will get I have already
drawn
as you can see it is same what they have
drawn on the piece of paper now let us
consider the resistance so resistance as
you can see this is the current how the
resistance will vary resistance
expression you can get by dividing the
voltage across the devices device by the
current and you can see the N Mo's
transistor will turn off here so it is
in linear mode so resistances you can
see gradually increasing current is
reducing resistance is increasing and it
will become infinite or very high at
this point when it changes switches from
region to region 3 on the other hand for
the P Mo's transistor it is in
saturation mode but current will keep on
decreasing because of the reduction in
the value of the gate voltage so gate
voltage is reducing so I mean sorry
drain voltage will be reducing and the
RP resistance value will be like this
current will remain same drain voltage
is reducing and resistance is reducing
and it will be constant because in the
linear mode resistance will remain same
so you can see we can combine these two
together because they are in parallel
these two devices are in parallel so
some of these two parallel combination
of these resistors will be like this so
you can see here the current that will
be passing through the resistor is like
this more or less constant okay we can
now consider another situation where you
know the input is earlier we have seen
input is changing from low to high
now input is suddenly changing suddenly
changed from high to low so in this case
output will gradually discharge assuming
that initially it will be high and then
gradually discharge to zero so it will
gradually reduce from zero to and VDD to
0
so as it goes from VDD to 0 what will be
the state of these three transistors
again you will see the operation will be
can be divided by dividing the operation
I mean the entire region into three
parts in the region 1 it will be equal
the V output will be equal to I mean
both NMOS and PMO's transistors Ahrens
are in saturation initially both of them
will be in saturation because you know
the output here it is VDD and here it is
zero so let me draw it so that I can
explain it a little better way so this
is your P Mo's transistor this is your n
MOS transistor so initially here it is 0
volt it has applied 0 volt you have
applied VDD both the and this tests are
on and initially here it is VDD then
what will be the condition so you can
see this transistor now will be always
on P n Mo's transistors will be always
on contrary to P Mo's transistor that
was always on in the previous case and
this this transistor will be on also on
initially because here it is VDD so this
is the source this is the drain and this
is the gate of P Mo's transistor on the
other hand this is the source this is
the gate gate and he is the drain of
this N Mo's transistor so initially all
both are in saturation as it is written
here but as the output voltage so this
is connected to VDD and he's connected
to 0 so as the voltage reduces to VDD
minus VT then this transistor switches
from saturation to linear mode of course
this transistor remains in saturation so
because you know that gate to gate to
source voltage and drain to source
voltage is
you know the difference is now VDD minus
VT so this this goes to saturation to
linear mode as it is written here in MOS
in linear region and Prima's in
saturation region when the output
voltage is going from VDD to minus VTP
and finally in the region 3 when the
output is VDD minus VTP n MOS in linear
region it remains in linear region and P
MOS in cutoff region so you can see the
P Mo's continues to operate continues to
remain on but P Mo's transistor turns
off so as it is shown in this diagram
this is how it happens
region 1 V output is less than VT n so
the n MOS transistors remains in
saturation for both region 1 and region
2 but the free Mo's transistor turns off
here and at this point when the output
is will be minus VT P and so you can see
the the operation is somewhat similar
but the role of the P Mo's and n MOS
transistor changes in this particular
case okay and accordingly we have just
like the previous case current exponent
is drawn this is the p MOS transistor
current this is the in MOS transistor
current and these are some of the two
currents and similarly the resistance
also will be somewhat similar only
difference is the role of n Mo's and P
Mo's transistors because as you can see
the resistance is somewhat identical to
the previous case now let us consider
another very interesting case when the
output is a small capacitance you have
connected a small capacitance to the
output of the transmission gate so
whenever the output capacitance is small
what will happen as the input changes
from 0 to VDD
since the capacitance is
all it will charge very quickly so if it
is charged slowly then the output will
follow the input with a small difference
that means if the in this particular
case if this is the input if this is V
in output will be this is time and this
is V output so this it will be somewhat
like this that means the output will
follow the card follow the input voltage
but with a difference and in this
particular case again you can divide the
operation into three regions as the
input changes from 0 to VDD region 1 V
in is less than VT n n mos in
non-saturated P MOS in cutoff one
interesting point is here you can see
voltage difference is always very small
between the our input and output and as
a consequence the transistors will never
be in saturation mode because you
require a high voltage across it for the
transistors to remain in saturation mode
that's why initially n MOS in
non-saturated Remos is cut off then
again as you go to region 2 then n MOS
in non-saturated and p MOS is non
saturated and as you go to region 3 n
MOS is cut off and p MOS in
non-saturated as it is shown here so VT
n 2 VT P absolute value of V DDH will be
actually it will be VT P and this is
your V DD so you can see here the
current for the two transistors are
shown here for the N Mo's transistors
current reduces quadratically here it is
shown I mean linear table will be a
quadratic line so it will it will reduce
quadratically for n MOS P Mo's
transistor the current will pick up
quadratically after this region so it
will turn on here initially we have seen
it was off so in the first part it was
off then it will build up quadratically
because the gate voltage is increasing
on the other end for n Mo's transistor
it will decrease quadratically because
we get voltage is reducing gradually
okay because input is linearly
increasing so this will be the current
that will be passing similarly we can
find out the equivalent resistances this
is the resistance of the PMO's
transistor initially it will be very
high because it was off in this region
then it is it will reduce gradually for
n MOS transistors initially it will be
low then it will increase and it will
become very high or infinite as it
reaches goes from 3 & 2 to region 3 and
the current will be either the parallel
hull of the resistance is more or less
same as you can see it remains constant
so we can summarize what you have
discussed today we have we have seen
most ancestors can be used as switches
of course with some limitations and
transmission gate profiles near optimal
switch as you have seen it is close to
closer to ideal then we have seen in
case of transmission gate to parallel
transistor supply current to the load
and behavior of transmission gate
driving a large capacitive load has been
discussed in detail behavior of a
transmission gate driving a small
capacitive load it will be small here is
a type of small capacitive load has been
discussed in detail so with this we have
come to the end of today's lecture and
our discussion on MOS transistors and as
we are following the bottom-up approach
in the next class we shall discuss the
operation of MOS inverters so we shall
start discussing on MOS inverters
starting from next class thank you