Main Memory Organization Computer Science Engineering (CSE) Notes | EduRev

Computer Architecture & Organisation (CAO)

Computer Science Engineering (CSE) : Main Memory Organization Computer Science Engineering (CSE) Notes | EduRev

The document Main Memory Organization Computer Science Engineering (CSE) Notes | EduRev is a part of the Computer Science Engineering (CSE) Course Computer Architecture & Organisation (CAO).
All you need of Computer Science Engineering (CSE) at this link: Computer Science Engineering (CSE)

Main Memory Organization
 Main memory unit is the storage unit, There are several location for storing information in the main memory module.

The capacity of a memory module is specified by the number of memory location and the information stored in each location.

A memory module of capacity 16 X 4 indicates that, there are 16 location in the memory module and in each location, we can store 4 bit of information.

We have to know how to indicate or point to a specific memory location. This is done by address of the memory location.

We need two operation to work with memory.

READ   Operation: This operation is to retrive the data from memory and bring it to CPU register

WRITE Operation: This operation is to store the data to a memory location from CPU register

We need some mechanism to distinguish these two operations READ and WRITE.

With the help of one signal line, we can differentiate these two operations. If the content of this signal line is

0,    we say that we will do a READ operation; and if it is
1,    then it is a WRITE operation.

To transfer the data from CPU to memory module and vice-versa, we need some connection. This is termed as DATA BUS.

The size of the data bus indicate how many bit we can transfer at a time. Size of data bus is mainly specified by the data storage capacity of each location of memory module.

We have to resolve the issues how to specify a particular memory location where we want to store our data or from where we want to retrive the data.

This can be done by the memory address. Each location can be specified with the help of a binary address.

If we use 4 signal lines, we have 16 different combinations in these four lines, provided we use two signal values only (say 0 and 1).

To distingush 16 location, we need four signal lines. These signal lines use to identify a memory location is termed as ADDRESS BUS. Size of address bus depends on the memory size. For a memory module of capacity of 2n location, we need n address lines, that is, an address bus of size n.  

We use a address decoder to decode the address that are present in address bus

As for example, consider a memory module of 16 location and each location can store 4 bit of information
The size of address bus is   4 bit and the size of the data bus is  4 bit
The size of address decoder is   4 X 16.

There is a control signal named R/W.
If   R/W  =  0,    we perform a  READ    operation and
if   R/W  =  1,    we perform a  WRITE   operation

If the contents of address bus is  0101  and contents of data bus is 1100 and R/W = 1, then 1100 will bewritten in location 5.

If the contents of address bus is 1011 and R/W=0, then the contents of location 1011 will be placed in data bus

Offer running on EduRev: Apply code STAYHOME200 to get INR 200 off on our premium plan EduRev Infinity!

Related Searches

Previous Year Questions with Solutions

,

past year papers

,

Exam

,

MCQs

,

study material

,

Objective type Questions

,

practice quizzes

,

video lectures

,

Viva Questions

,

Important questions

,

Semester Notes

,

Sample Paper

,

ppt

,

pdf

,

Summary

,

Main Memory Organization Computer Science Engineering (CSE) Notes | EduRev

,

Main Memory Organization Computer Science Engineering (CSE) Notes | EduRev

,

shortcuts and tricks

,

Main Memory Organization Computer Science Engineering (CSE) Notes | EduRev

,

Free

,

mock tests for examination

,

Extra Questions

;