Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

Digital Electronics

Electrical Engineering (EE) : Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

The document Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course Digital Electronics.
All you need of Electrical Engineering (EE) at this link: Electrical Engineering (EE)

The D Type Master Slave Flip-Flop

Yet a further version of the D Type flip-flop is shown in Fig. 5.3.6 where two D type flip-flops are incorporated in a single device, this is the D type master-slave flip-flop. Circuit symbols for the master-slave device are very similar to those for edgetriggered flip-flops, but are now divided into two sections by a dotted line, as also illustrated in Fig 5.3.6.

FF1 (the master flip-flop) is a positive edge triggered device, and an inverted version of the CK pulse is fed from the main CK input to FF2 (the slave), also positive edge triggered. Notice that although the clock inputs on the circuit symbols suggest that this is a negative edge triggered device, data is actually taken into FF1 on the POSITIVE going edge of the CK pulse. The data also of course appears at q1 at this time, but as the CK pulse is inverted at ck2, FF2 is seeing a falling edge at the same time, so ignores the data on d2.

After the positive going edge of the external CK pulse, FF1 ignores any further data at D, and at the negative going edge of the external CK pulse, the data being held at q1 is taken into the d2 input of FF2 which now sees a positive going edge of the inverted CK pulse. Therefore data is taken into D at the positive going (rising) edge of the CK pulse, and then appears at Q at the negative going (falling) edge of the CK pulse.

 

Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

 

Considering the master slave flip-flop as a single device, the relationship between the clock (CK) input and the Q output does look rather like a negative edge triggered device, as any change in the output occurs at the falling edge of the clock pulse. However, as illustrated in Fig. 5.3.7 this is not really negative edge triggering, because the data appearing at Q as the clock pulse returns to logic 0, is actually the data that was present at input D at the RISING edge of the CK pulse. Any further changes that may occur in data at the D input during the clock pulse are ignored. D type master-slave flip-flops are also available with asynchronous Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev  inputs making it a very versatile device indeed.

 

Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

Offer running on EduRev: Apply code STAYHOME200 to get INR 200 off on our premium plan EduRev Infinity!

Related Searches

Previous Year Questions with Solutions

,

study material

,

Exam

,

Summary

,

Free

,

past year papers

,

Important questions

,

Semester Notes

,

practice quizzes

,

shortcuts and tricks

,

Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

,

mock tests for examination

,

Viva Questions

,

Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

,

Sample Paper

,

Master Slave Flip-Flop - S-R Flip Flops Electrical Engineering (EE) Notes | EduRev

,

Objective type Questions

,

pdf

,

ppt

,

video lectures

,

MCQs

,

Extra Questions

;