Semiconductor Memory Interfacing
Semiconductor memories are of two types:
- RAM (Random Access Memory)
- ROM (Read Only Memory).
Static RAM Interfacing
16-Bit Memory Interface
- The semiconductor RAMs are of broadly two types-static RAM and dynamic RAM. The semiconductor memories are organized as two-dimensional arrays of memory locations.
Example: 4K x 8 or 4K byte memory contains 4096 locations, where each location contains 8-bit data and only one of the 4096 locations can be selected at a time. Obviously, for addressing 4K bytes of memory, twelve address lines are required.
- In general, to address a memory location out of N memory locations, we will require at least n bits of address, i.e. n address lines where n = Log2 N.
- Thus if the microprocessor has n address lines, then it is able to address at the most N locations of memory, where 2n = N.
- However, if out of N locations only P memory locations are to be interfaced, then the least significant p address lines out of the available n lines can be directly connected from the microprocessor to the memory chip while the remaining (n-p) higher-order address lines may be used for address decoding (as inputs to the chip selection logic).
- The memory address depends upon the hardware circuit used for decoding the chip select The output of the decoding circuit is connected with the pin of the memory chip.
The general procedure of static memory interfacing with 8086 is briefly described as follows:
- Arrange the available memory chips so as to obtain 16-bit data bus width. The upper 8-bit bank is called ‘odd address memory bank’ and the lower 8-bit bank is called ‘even address memory bank’.
- Connect available memory address lines of memory chips with those of the microprocessor and also connect the memory and inputs to the corresponding processor control signals. Connect the 16-bit data bus of the memory bank with that of the microprocessor 8086.
- The remaining address lines of the microprocessor, and A0 are used for decoding the required chip select signals for the odd and even memory banks. of memory is derived from the O/P of the decoding circuit.
As a good and efficient interfacing practice, the address map of the system should be continuous as far as possible, i.e. there should be no windows in the map. A memory location should have a single address corresponding to it, i.e. absolute decoding should be preferred, and minimum hardware should be used for decoding. In a number of cases, linear decoding may be used to minimise the required hardware.
Question 1:The semiconductor memories are organised as __________ dimension(s) of array of memory locations.
The semiconductor memories are organised as two dimensions of an array which consists of rows and columns.
Let us now consider a few example problems on memory interfacing with 8086.
Interface two 4K x 8 EPROMS and two 4K x 8 RAM chips with 8086. Select suitable maps.
Solution. We know that, after reset, the IP and CS are initialised to form address FFFFOH. Hence, this address must lie in the EPROM. The address of RAM may be selected anywhere in the 1MB address space of 8086, but we will select the RAM address such that the address map of the system is continuous, as shown in Table.
Table: Memory Map for Problem 1.
- Total 8K bytes of EPROM need 13 address lines A0- A12 (since 213 = 8K). Address lines A13 - A19 are used for decoding to generate the chip select. The BHE signal goes low when a transfer is at odd address or higher byte of data is to be accessed. Let us assume that the latched address, and demultiplexed data lines are readily available for interfacing. Figure 5.1 shows the interfacing diagram for the memory system.
- The memory system in this example contains in total four 4K x 8 memory chips.
The two 4K x 8 chips of RAM and ROM are arranged in parallel to obtain 16-bit data bus width. If A0 is 0, i.e. the address is even and is in RAM, then the lower RAM chip is selected indicating 8-bit transfer at an even address.
- If A0 is 1, i.e. the address is odd and is in RAM, the goes low, the upper RAM chip is selected, further indicating that the 8-bit transfer is at an odd address. If the selected addresses are in ROM, the respective ROM chips are selected. If at a time A0 and both are 0, both the RAM or ROM chips are selected, i.e. the data transfer is of 16 bits. The selection of chips here takes place as shown in Table.
Design an interface between 8086 CPU and two chips of 16K x 8 EPROM and two chips of 32K x 8 RAM. Select the starting address of EPROM suitably. The RAM address must start at 00000H.
Solution. The last address in the map of 8086 is FFFFFH. After resetting, the processor starts from FFFFOH. Hence this address must lie in the address range of EPROM. Figure below shows the interfacing diagram, and Table below shows complete map of the system.
Table: Address Map for Problem 2.
It is better not to use a decoder to implement the above map because it is not continuous, i.e. there is some unused address space between the last RAM address (0FFFFH) and the first EPROM address F8000H). Hence the logic is implemented using logic gates, as shown below.
It is required to interface two chips of 32K x 8 ROM and four chips of 32K x 8 RAM with 8086, according to the following map.
ROM 1 and 2 FOOOOH - FFFFFH, RAM 1 and 2 D0000H - DFFFFH
RAM 3 and 4 E0000H - EFFFFH
Show the implementation of this memory system.
Solution. Let us write the memory map of the system as shown in Table.
The implementation of the above map is shown in below using the same technique as in Problem 1 and Problem 2. All the address, data and control signals are assumed to be readily available.