Comparison between Memory mapped I/O and Peripheral mapped I/O
Instructions Sets & Data Formats
- An “Instruction” is a binary pattern designed inside a microprocessor to perform a specified function. In another words we can say An Instruction is a command given to the microprocessor to perform a given task on specified data.
- Each instructions has two parts:
- One is the task to be performed, called the “operation code” (OPCODE).
- And the second is the data to be operated on, called the “OPERAND”.
- The operand (or data) may include 8-bit (or 16- bit) data, on internal register, a memory location, or 8-bit (or 16-bit) address.
- It is the collection of instructions of microprocessor, that determines what functions that microprocessor can perform.
- Some important aspects of the instruction set are noted below:
- In data transfer, the contents of the source are not destroyed; only the contents of the destination are changed.
- An I/O device can transfer or receive data from the accumulator but not from other registers (except for the memory-mapped I/O device). -
- Arithmetic and logical operations are performed with the contents of tho-aceumulator. and the results are stored in the accumulator (with some; exceptions).
- Any register including memory can be used for increment and decrement. ;
- A program sequence can be changed either conditionally or by testing for a given data condition.
- In some instructions data: is implied. The most instructions of this type operate on the content of the aecumulator.
Classification of Instructions Set of 8085 Microprocessor
The Addressing Modes
The various formats for specifying operands are called the ADDRESSING MODES. For 8085, they are:
Data is present in the instruction. Load the immediate data to the destination provided.
Example: MVI R, data
Register addressing: ....
Data is provided through the registers.
Example: MOV Rd, Rs
Used to accept data from outside devices to store in the accumulator or send the data stored in the accumulator to the outside device. Accept the data from the port 00H and store them into the accumulator or Send the data from the accumulator to the port Of_
Example: INOOH or OUT 01H.
This means that the Effective Address is calculated by the processor. And the contents of the address (and the one following) is used to form a second address. The second address is where the data is stored.
Memory Accessing & Addressing Modes
- The MPU can’t just issues an address on the address bus following it up either by sending data or be ready to receive data from any of the peripherals at only instant of time as it may be already engaged.
- For this a signal is sent to the peripheral to know its status, common status signals are BUSY and READY.
Development of Data Transfer Schemes (DTS)
- A microprocessor-based system or a computer may have several I/O devices of different speed. A slow I/O device can not transfer data when microprocessor issues instruction for the same because it takes some time to get ready.
- To solve this problem of speed mismatch between a microprocessor and I/O devices a number of data transfer techniques have been developed.
- Programmed data transfer schemes are controlled by the CPU.
- Data are transferred from an I/O device to the CPU (or to the memory through the CPU) or vice versa under the control of programs Which reside in the memory.
- Programmed DJS are employed when small amount of data are to be transferred
- Synchronous means “at the same time”. In this D TS the device which sends data and the device which receives data are synchronised with the same clock.
- The data transfer with I/O devices is performed executing IN or OUT instruction? for I/O mapped I/O devices or using memory:read/write instructions for memory mapped I/O devices.
- The I/O devices compatible with microprocessors in speed are usually not available. Hence, this technique of data transfer is rarely used for I/O devices.
- Asynchronous means “at irregular intervals”. In this DTS, data transfer is not based on pre-determined timing pattern.
- This technique of data transfer is used when the speed of an I/O device does not match the speed of the microprocessor, and the timing characteristic of I/O device is not predictable.
- In this technique the status of the I/O device i.e. whether the device is ready or not, is checked by the microprocessor before the data are transferred.
- Asynchronous data transfer is used for slow I/O devices. This technique is an inefficient technique because the precious time of the microprocessor is wasted in waiting.
- Two ways to achieve asynchronous DTS are:
- Strobe control hand shaking method of DTS
- DMA Data Transfer Scheme (DMA-DTS)
Strobe control hand shaking method of DTS
- Also, the “HANDSHAKING CONTROL” operates as follows:
- The CPU interrogates the I/O module to check the status of the required device (peripheral).
- The I/O module replies to the device status.
- If free, the peripheral sends the data and a DATA READY signal to the I/O port
- The CPU determines that the DATA READY signal is active. A latch holds the DATA ~ READY signal until the CPU reads it.
- The CPU accepts the data and sends an Data Accepted signal (DACC) by way of acknowledgment.
- DATA READY line is reset to be ready to receive further data.
DMA Data Transfer Scheme (DMA-DTS): .
- In DMA-D’I S, MRU doesn’t participate because data are directly transferred from an I/O device to the memory or vice-versa.
- The MPU communicates with the controller by using the chip select line, Buses and Control signals. Examples of DMA controller chips are: Intel 8237A, 8257 etc.
- DMA-DTS is a faster scheme as compared to programmed DTS.
- It is used to transfer data from “mass storage devices” (hard disks, floppy disks etc). It is also used for high-speed printers.
- Once the controller has gained control, it plays the role of a processor for data transfer as:
- The DMA controller chip puts the MPU in a HOLD state by means of the HOLD control signal. This is an active high input signal.
- The MPU then stops executing the program and disconnects the address, data and memory control lines from its bus by placing them on a high impedance state. The microprocessor is totally disabled during DMA.
- The MPU sends a DMA acknowledge signal when the DMA takes control of the address bus and control bus to put data on the RAM from the I/O device, “(his is also an active high signal.
- When once the DMA completes transfer of data into or out of memory, the DMA controller transfers back the control of the buses to the MPU by releasing the HOLD slate when it does low.
Burst Mode of DMA Data Transfer:
- A scheme of DMA data transfer, . which the I/O % device withdraws the DMA request only after all the data bytes have been transferred, is called burst mode of data transfer.
- By this technique a block of data is transferred.
- This technique is employed by magnetic disks drives.
Cycle stealing mode of DMA data transit r
- In this technique a long block of data is transferrea by a sequence of DMA’cycles.
- In this method after transferring one byte or several bytes the I/O device withdraws DMA request.
- This method reduce interference in CPU’s activities.
- The interference can be eliminated completely by designing an interfacing circuitry which can steal bus cycle for DMA data transfer only when the CPU is not using the system bus.
- This modes of DTS has highest efficiency.
- Interrupt is a process where an external device can get the attention of the microprocessor.
- The process starts from the I/O device
- The process is asynchronous.
- Interrupts can be classified into two types:
- Maskable (can be delayed)
- Non-Maskable (can not be delayed)
- Interrupts can also be classified into;
- Vectored (the address of the service routine is hard-wired)
- Non-vectored (the address of the service routine needs to be supplied ex externally)
The 8085 Interrupt
- The maskable interrupt process in the 8085 is controlled by a single flip flop inside the microprocessor. This interrupt Enable flip flop is controlled using the two instructions “EI” and “DI”
- The 8085 has a single Non-maskable interrupt.
- The non-maskable interrupt is not affected by the value of the Interrupt Enable flip flop.
The 8085 has 5 interrupt inputs:
- The INTR input.
- The INTR input is the only non vectored interrupt.
- INTR is maskable using the EI/DI instruction pair.
- RST 5.5, RST 6.5, RST 7.5 are all automatically vectored.
- RST 5.5, RST 6.5, and RST 7.5 are all maskable.
- TRAP is the only non-maskable interrupt in the 8085
- TRAP is also automatically vectored
The 8085 Interrupts
|INTR||YES||DI / EI||No||NO||Level Senstive|
|RST5.5 / RST6.5||YES||DI / EI SIM||YES||NO||Level Senstive|
|RST7.5||YES||DI / EI SIM||YES||YES||Edge Senstive|
|TRAP||No||None||YES||YES||Level & Edge|
| || || || || || |
A microprocessor includes ALU, register arrays and control circuits on a single chip.
A device that includes microprocessor, memory and input and output signal lines on a single chip, fabricated
using VLSI technology.
Architecture of 8085 Microprocessor.
16 bit higher level processors (8086):
Primary objective of 16 bit microprocessor.
i. Increase memory addressing capacity.
ii. Increase execution speed.
iii. Provide a powerful instruction set.
iv. Facilitate programming in high level languages.
v. Function in a multi-processor environment.
Architecture : (8086)
Tow operating modes of processor, when singla is high operate in minimum mode and when it is low then
in maximum mode.
TEST: Used to synchronize operations of multiple processors in a system.
DEN-Data Enable: Active low output signal that is generally connected to bi-directional buffer to isolate MOU from the system bus.
This is also connected to a bi-directional buffer to enable data flow.
M/IO-Memory and Input/Output:
It indicates whether the processor cycle is an input/output operation or a memory operation. Low signal
activate I/O mode & high signal activate memory operation.
AD15 to AD0: address data bus : These lines constitute the time multiplexed M/IO addres and data bus.
ALE: Address Latch Enable: A HIGH on this line cause the lower order 16 bit address bus to be latched.
READY : It is the acknowledgement from the addressed memory or I/O device that it will complete the data
INTR:interrupt request : It is a level triggered input which is sampled during the last clock cycle of each
instruction to determine if the processor should enter into an interrupt acknoledge operation. It can be internally
masked by software resetting the interrupt enable bit.
INTA: Interrupt Acknowledge from the microprocessor.
NMI: Non-Maskable Interrupt : It is an edge triggered input which causes an interrupt request to the MP.
It is not maskable internally by softwere.
RESET : Cause the processor to immediately terminate its present activity. The signal must be active high for
at least four clock cycles.
HOLD : This pin is used by external devices to gain control of the buses.
HLDA : When the HOLD signal is activated by an external device, the 8086 stops executing instructions and
stops usign the buses.
Architecture of 8086 Microprocessor:
BHE-Bus High Enable:
Active low signal used only in 8086 processor to enable the high order byte of 16 bit data.
- 8086 Processor includes two processing units called execution unit and BUS interface unit.
- 8086 Processor divides the work between two units and process it simultaneous to speed up the execution.
- BIU fetches the instructions and places them in a queue and the EU continuously executes them until the queue is empty.
Programming model: 8086 includes four 16 - bit general purpose registers
- The Next registers (16 bit) used as memory pointers: foru
SP (Stack pointer) BP (Base Pointer)
SI (Source Index) DI(Destination Index)
- Next foru segment registers are:
- Last 16 it register IP (Instruction pointer) in 8086, which is same as PC (Program Counter) in 8065.
- The flag register includes nine, flags, four are new to 8086, and these are:
OF-OVERFLOW: This is used in signed numbers when the result of signed number operation is too large, this
flag is set.
DF-Direction Flag : Used to enable or direction (increment/ decrement ) of string operations.
IF - Interrupt Flag: used to enable or disable external maskable interrupt requests.
TF - Trap Flag: used for single stepping instructions.
- The memory addresses in 8086 system are specified in three formats:
- The offset address is the address of an instruction in reference to base address.
- The logical address is combination of a segment and offset address.
- Physical address is a 20 bit address, the beginning address of instruction code by combining the address in CS and IP. It is not an addition but the processor shifts the address in CS by four bits (One Hex) to left and the address in IP.
Segment register address: 1200 H, Instruction pointer address: 0000H
Then: Offset address → 0000 H
Logical address → 1200:000
Physical address →
Physical Address 12000