Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev

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Computer Science Engineering (CSE) : Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev

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Minimum Mode Interface


  • When the Minimum mode operation is selected, the 8086 provides all control signals needed to implement the memory and I/O interface.
  • The minimum mode signal can be divided into the following basic groups :


  1.  Address/data bus
  2.  Status
  3.  Contro
  4.  Interrupt and
  5. DMA.

Each and every group is explained clearly.

Address/Data Bus:

  • These lines serve two functions. As an address bus is 20 bits long and consists of signal lines A0 through A19. A19 represents the MSB and A0 LSB. A 20bit address gives the 8086 a 1Mbyte memory address space. More over it has an independent I/O address space which is 64K bytes in length.
  • The 16 data bus lines D0 through D15 are actually multiplexed with address lines A0 through A15 respectively. By multiplexed we mean that the bus work as an address bus during first machine cycle and as a data bus during next machine cycles.
  • D15 is the MSB and D0 LSB. When acting as a data bus, they carry read/write data for memory, input/output data for I/O devices, and interrupt type codes from an interrupt controller.

Status signal:

  • The four most significant address lines A19 through A16 are also multiplexed but in this case with status signals S6 through S3.
  • These status bits are output on the bus at the same time that data are transferred over the other bus lines.

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev

  • Bit S4 and S3 together from a 2 bit binary code that identifies which of the 8086 internal segment registers is used to generate the physical address that was output on the address bus during the current bus cycle. Code S4S3 = 00 identifies a register known as extra segment register as the source of the segment address.
  • Status line S5 reflects the status of another internal characteristic of the 8086. It is the logic level of the internal enable flag. The last status bit S6 is always at the logic 0 level. 

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev  

Control Signals:

  • The control signals are provided to support the 8086 memory I/O interfaces. They control functions such as when the bus is to carry a valid address in which direction data are to be transferred over the bus, when valid write data are on the bus and when to put read data on the system bus.
  • ALE is a pulse to logic 1 that signals external circuitry when a valid address word is on the bus. This address must be latched in external circuitry on the 1-to-0 edge of the pulse at ALE.
  • Another control signal that is produced during the bus cycle is BHE bank high enable.Logic 0 on this used as a memory enable signal for the most significant byte half of the data bus D8 through D1. These lines also serve a second function, which is as the S7 status line.
  • Using the M/IO and DT/R lines, the 8086 signals which type of bus cycle is in progress and in which direction data are to be transferred over the bus. The logic level of M/IO tells external circuitry whether a memory or I/O transfer is taking place over the bus.
    Logic 1 at this output signals a memory operation and logic 0 an I/O operation.
  • The direction of data transfer over the bus is signaled by the logic level output at DT/R.
    When this line is logic 1 during the data transfer part of a bus cycle, the bus is in the transmit mode. Therefore, data are either written into memory or output to an I/O device.On the other hand, logic 0 at DT/R signals that the bus is in the receive mode. This corresponds to reading data from memory or input of data from an input port.
  • The signals read RD and write WR indicates that a read bus cycle or a write bus cycle is in progress. The 8086 switches WR to logic 0 to signal external device that valid write or output data are on the bus.
  • On the other hand, RD indicates that the 8086 is performing a read of data of the bus.
    During read operations, one other control signal is also supplied. This is DEN (data enable) and it signals external devices when they should put data on the bus. There is one other control signal that is involved with the memory and I/O interface. This is the READY signal.
  • READY signal is used to insert wait states into the bus cycle such that it is extended by a number of clock periods. This signal is provided by an external clock generator device and can be supplied by the memory or I/O sub-system to signal the 8086 when they are ready to permit the data transfer to be completed.

Interrupt signals:


  • The key interrupt interface signals are interrupt request (INTR) and interrupt acknowledge (INTA)
  •  INTR is an input to the 8086 that can be used by an external device to signal that it need to be serviced.
  •  Logic 1 at INTR represents an active interrupt request. When an interrupt request has been recognized by the 8086, it indicates this fact to external circuit with pulse to logic 0 at the INTA output.
  • The TEST input is also related to the external interrupt interface. Execution of a WAIT instruction causes the 8086 to check the logic level at the TEST input.
  • If the logic 1 is found, the MPU suspend operation and goes into the idle state. The 8086 no longer executes instructions; instead it repeatedly checks the logic level of the TEST input waiting for its transition back to logic 0.
  • As TEST switches to 0, execution resume with the next instruction in the program.This feature can be used to synchronize the operation of the 8086 to an event in external hardware.
  • There are two more inputs in the interrupt interface: the nonmaskable interrupt NMI and the reset interrupt RESET.
  • On the 0-to-1 transition of NMI control is passed to a nonmaskable interrupt service routine. The RESET input is used to provide a hardware reset for the 8086. Switching RESET to logic 0 initializes the internal register of the 8086 and initiates a reset service routine.

 DMA Interface signals:

  •  The direct memory access DMA interface of the 8086 minimum mode consist of the HOLD and HLDA signals.
  • When an external device wants to take control of the system bus, it signals to the 8086 by switching HOLD to the logic 1 level. At the completion of the current bus cycle, the 8086 enters the hold state. In the hold state, signal lines AD0 through AD15, A16/S3 through A19/S6, BHE, M/IO, DT/R, RD, WR, DEN and INTR are all in the high Z state.
  • The 8086 signals external device that it is in this state by switching its HLDA output to logic 1 level.

Maximum Mode Interface

  • When the 8086  is  set for the maximum-mode configuration, it  provides signals for implementing a multiprocessor / coprocessor system environment.
  • By multiprocessor environment we mean that one microprocessor exists in the system and that each processor is executing its own program.
  • Usually in this type of system environment, there are some system resources that are common to all processors. They are called as global resources. There are also other resources that are assigned to specific processors. These are known as local or private resources.
  • Coprocessor also means that there is a second processor in the system. In these two processors does not access the bus at the same time. One passes the control of the system bus to the other and then may suspend its operation.
  • In the maximum-mode 8086 system, facilities are provided for implementing allocation of global resources and passing bus control to other microprocessor or coprocessor.

8288 Bus Controller – Bus Command and Control Signals:

  • 8086 does not directly provide all the signals that are required to control the memory, I/O and interrupt interfaces.

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev  

  • Specially the WR, M/IO, DT/R, DEN, ALE and INTA, signals are no longer produced by the 8086. Instead it outputs three status signals S0, S1, S2 prior to the initiation of each bus cycle. This 3- bit bus status code identifies which type of bus cycle is to follow.
  • S2S1S0 are input to the external bus controller device, the bus controller generates the appropriately timed command and control signals.
  • The 8288 produces one or two of these eight command signals for each bus cycles. For instance, when the 8086 outputs the code S2S1S0 equals 001; it indicates that an I/O read cycle is to be performed.

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev  

  • In the code 111 is output by the 8086, it is signaling that no bus activity is to take place.
  • The control outputs produced by the 8288 are DEN, DT/R and ALE. These 3 signals provide the same functions as those described for the minimum system mode.
  • This set of bus commands and control signals is compatible with the Multibus and industry standard for interfacing microprocessor systems.
  • The output of 8289 are bus arbitration signals:

Bus busy (BUSY), common bus request (CBRQ), bus priority out (BPRO), bus priority in (BPRN), bus request (BREQ) and bus clock (BCLK).

  • They correspond to the bus exchange signals of the Multibus and are used to lock other processor off the system bus during the execution of an instruction by the 8086.
  • In this way the processor can be assured of uninterrupted access to common system resources such as global memory.
  • Queue Status Signals: Two new signals that are produced by the 8086 in the maximum- mode system are queue status outputs QS0 and QS1. Together they form a 2-bit queue status code, QS1QS0.
  • Following table shows the four different queue status.
  • Local Bus Control Signal – Request / Grant Signals: In a maximum mode configuration, the minimum mode HOLD, HLDA interface is also changed


QS1QS0Queue Status
0 (Low)0Queue Empty. The queue has been reinitiated as a result of the execution of a transfer instruction.
01First Byte. The byte taken from the queue was the first byte of the instruction.
10Queue Empty. The queue has been reinitiated as a result of the execution of a transfer instruction.
11 (High)Subsequent Byte. The byte taken from the queue was the subsequent byte of the instruction.


  • These two are replaced by request/grant lines RQ/ GT0 and RQ/ GT1, respectively. They provide a prioritized bus access mechanism for accessing the local bus.


Definition: The meaning of ‘interrupts’ is to break the sequence of operation. While the CPU is executing a program, on ‘interrupt’ breaks the normal sequence of execution of instructions, diverts its execution to some other program called Interrupt Service Routine (ISR).After executing ISR , the control is transferred back again to the main program.
Interrupt processing is an alternative to polling.

Need for Interrupt: Interrupts are particularly useful when interfacing I/O devices that provide or require data at relatively low data transfer rate.

Types of Interrupts: There are two types of Interrupts in 8086. They are:

(i) Hardware Interrupts and

(ii) Software Interrupts

(i) Hardware Interrupts (External Interrupts). The Intel microprocessors support hardware interrupts through:

  • Two pins that allow interrupt requests, INTR and NMI
  • One pin that acknowledges, INTA, the interrupt requested on


  • INTR is a maskable hardware interrupt. The interrupt can be enabled/disabled using STI/CLI instructions or using more complicated method of updating the FLAGS register with the help of the POPF instruction.
  • When an interrupt occurs, the processor stores FLAGS register into stack, disables further interrupts, fetches from the bus one byte representing interrupt type, and jumps to interrupt processing routine address of which is stored in location 4 * <interrupt type>. Interrupt processing routine should return with the IRET instruction.
  • NMI is a non-maskable interrupt. Interrupt is processed in the same way as the INTR interrupt. Interrupt type of the NMI is 2, i.e. the address of the NMI processing routine is stored in location 0008h. This interrupt has higher priority than the maskable interrupt.
  • – Ex: NMI, INTR.

(ii) Software Interrupts (Internal Interrupts and Instructions) .Software interrupts can be caused by:

  • INT instruction - breakpoint interrupt. This is a type 3 interrupt.
  • INT <interrupt number> instruction - any one interrupt from available 256 interrupts.
  • INTO instruction - interrupt on overflow
  • Single-step interrupt - generated if the TF flag is set. This is a type 1 interrupt. When the CPU processes this interrupt it clears TF flag before calling the interrupt processing routine.
  • Processor exceptions: Divide Error (Type 0), Unused Opcode (type 6) and Escape opcode (type 7).
  • Software interrupt processing is the same as for the hardware interrupts.
  • - Ex: INT n (Software Instructions)
  • Control is provided through:


  1. IF and TF flag bits
  2. IRET and IRETD

 Performance of Software Interrupts

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev

  1.  It decrements SP by 2 and pushes the flag register on the stack.
  2.  Disables INTR by clearing the IF.
  3. It resets the TF in the flag Register.
  4. It decrements SP by 2 and pushes CS on the stack.
  5. It decrements SP by 2 and pushes IP on the stack.
  6. Fetch the ISR address from the interrupt vector table.

Interrupt Vector Table 

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRevMinimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev

Functions associated with INT00 to INT04

INT 00 (divide error)

  • INT00 is invoked by the microprocessor whenever there is an attempt to divide a number by zero.
  • ISR is responsible for displaying the message “Divide Error” on the screen

INT 01

  • For single stepping the trap flag must be 1
  • After execution of each instruction, 8086 automatically jumps to 00004H to fetch 4 bytes for CS: IP of the ISR.
  • The job of ISR is to dump the registers on to the screen

INT 02 (Non maskable Interrupt)

  • When ever NMI pin of the 8086 is activated by a high signal (5v), the CPU Jumps to physical memory location 00008 to fetch CS:IP of the ISR associated with NMI.

INT 03 (break point)

  • A break point is used to examine the CPU and memory after the execution of a group of Instructions.
  • It is one byte instruction whereas other instructions of the form “INT nn” are 2 byte instructions.

INT 04 (Signed number overflow)

  • There is an instruction associated with this INT 0 (interrupt on overflow).
  • If INT 0 is placed after a signed number arithmetic as IMUL or ADD the CPU will activate INT 04 if 0F = 1.
  • In case where 0F = 0, the INT 0 is not executed but is bypassed and acts as a NOP.

Performance of Hardware Interrupts

  • NMI : Non maskable interrupts - TYPE 2 Interrupt
  • INTR : Interrupt request - Between 20H and FFH 

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev  

Interrupt Priority Structure

Minimum and Maximum Mode Interface Computer Science Engineering (CSE) Notes | EduRev


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