Because voltages in digital circuits can be continually changing very rapidly between logic 1 and logic 0, (virtually between supply voltage and ground), they have the potential to produce a lot of noise, in the form of high frequency voltage spikes on the IC power supply lines.
To counteract this it is important to include effective decoupling, not only at the power supply unit, but also by connecting decoupling capacitors across the VDD and 0V connections at each IC. These capacitors are normally connected as physically close to the IC as possible, as shown in Fig. 3.3.2.
Despite these measures, it is possible that some noise will remain that could disturb the logic levels of digital signals. However logic ICs have a built in ‘Noise Margin’, illustrated in Fig. 3.3.3, This is the difference between the worst-case voltage ( VOH) for logic 1 at the output , which is 2.4V in the case of 74HCT, and the minimum voltage required for logic 1 to be recognised at the input (VIH), 2.0V in 74HCT. This difference (0.4V) should be enough to ensure that noise does not cause a wrong logic level to be seen by the 74HCT input; a similar noise margin is provided for logic 0 (VIL−VOL) as shown in Fig. 3.3.3.
It can be seen from Fig. 3.3.1 that different logic families have very different noise margins. The CMOS 74HC gates have a much wider noise margin than LS TTL or the TTL compatible 74HCT series, making them much more tolerant of noise. This is because the CMOS outputs are normally driven very close to VDD or 0V as very little current is drawn from a CMOS output to drive any CMOS inputs connected to it.
In both CMOS and TTL ranges it is important that the central (white) range of voltages in Fig. 3.3.1 is avoided as much as possible. This is done by ensuring that switching between 1 and 0 is as fast as possible. If the IC is operating within the ‘invalid range’, power consumption increases dramatically. When the output voltage is close to the supply voltage, current is almost zero and therefore power (V x I) is very low. Similarly when the output is close to 0V but maximum current is flowing, V x I is again very low. Power consumption is at its highest when both voltage and current are around the mid range, and operating the ICs in this range would substantially increase the heat dissipated by the IC.
However, any unused inputs on CMOS ICs will tend to float to a mid voltage level, causing power dissipation to increase. To avoid problems with floating CMOS inputs, they should therefore be connected to either supply or ground, either directly or via a resistor, so they are not allowed to ‘float’ and cause excessive power consumption. This is not absolutely necessary, (though good practice), with TTL ICs as any unused TTL inputs will float up to logic 1.
Notice that ECL/PECL gates operate exclusively in this mid range area; this is why power consumption in these families is higher than in TTL or CMOS. However the close proximity of the logic 1 and logic 0 values in ECL allows for much higher switching speeds. This operation also gives ECL a much narrower noise margin however, making these chips more susceptible to noise. This is the reason for ECL having its positive supply tied to 0V, which is generally less noisy than sharing a positive supply with many other ICs.
The differences in the output voltage and/or current levels for TTL and the CMOS gates can affect circuit operation if both bipolar and CMOS logic families are used in the same circuit (e.g. LS TTL and HCT or CMOS), or if an older TTL IC is replaced by an ‘equivalent’ HCT chip during repairs or upgrading.
When mixing logic families it is important to consult input and output specifications such as those listed in Table 3.3.1 to ensure that the input and output conditions are compatible. The data in Table 3.3.1 shows typical input and output values for logic families, but particular ICs within a family or sub-family, and ICs from different suppliers will differ. The only way to be sure of complete compatibility is to consult the manufacturers data sheets for the ICs concerned.
Generally TTL outputs will interface to other TTL family inputs, and to 74HCT, which has TTL level inputs and CMOS level outputs.
The 74HCT outputs will interface to CMOS inputs provided both ICs are working from a common +VDD supply. This should not be a problem with the 74HC series, as it will operate on 5V supplies.
Connecting a TTL output to a CMOS HC input may work if TTL input is not heavily loaded. A problem occurs however when more current is sourced by the TTL logic 1 output. Its output voltage (VOH) depends on the current being drawn from it and will vary from around 3.3V with no load current, down to about 2.4V when the output is sourcing around 400µA. As the HC gate input requires a minimum input voltage (VIH) of 3.2V there is a chance that at some output current between 0 and 400µA the TTL output will fall below 3.2V, and fail to be recognised as logic 1 by an HC input using its maximum supply voltage of 16V. Even if the HC supply is reduced to 4.5V there will still be a chance of mismatch.
The remedy is to fit a pull up resistor from the TTL output to Vcc as shown in Fig 3.3.4, which will increase the TTL output voltage (VOH) sufficiently to ensure correct interfacing. The value of the resistor should be between 1K and 2K ohms, the optimum value depending on the Fan out factor of the TTL gate and the number of gates being driven, the less current the output is sourcing, the lower the value of pull-up resistor needed.
With the older +5V TTL and +3V to +18V 4000 CMOS families the logic levels must be shifted considerably. For this purpose, a level translator IC such as the MC14504B from ON Semiconductor will provide level shifting for up to six ICs with VCC or VDD at any value between +0.5V and +18V. An alternative solution to level translation is to use Open Collector ICs.
ECL to TTL interfacing is carried out by ICs such as the MC10ELT25 from ON Semiconductor.