P-N Junction Diode | Solid State Physics, Devices & Electronics PDF Download

P-N Junction Diode 

Semiconductor Diode  

In an n-type material the electron is called the majority carrier and the hole the minority carrier. In an p-type material the holes are the majority carrier and the electrons are minority carrier.
If the two materials are “joined” the electrons and holes in the region of the junction will combine resulting in a lack of carriers in the region near the junction. This region of uncovered positive and negative ions is called the depletion region due to the depletion of mobile carriers in this region.  
Since the diode is two terminal devices, the application of a voltage across its terminals leaves three possibilities: no bias (V_D = 0V ) , forward bias (V_D > 0V ) and reverse bias (V_D<0V). Each is a condition that will result in a response that one must clearly understand if the device is to be applied effectively.

➤ No Applied Bias

Under no bias condition, any minority carriers (holes) in the n-type material that find themselves within the depletion region will pass directly into the p-type material. The closer the minority carrier is to the junction, the greater the attraction for the layer of negative ions and the less the opposition of the positive ions in the depletion region of the n-type material. For further discussions we shall assume that all the minority carriers in the n-type material that find themselves in the depletion region due to their random motion will pass directly into the p-type material. Similar discussion can be applied to the minority carriers (electrons) of the p-type material.  
The majority carriers (electrons) of the n-type material must overcome the attractive forces of the layer of positive ions in the n-type material and the shield of negative ions in the p-type material in order to migrate into the area beyond the depletion region of the   p-type material. Again the same type of discussion can be applied to the majority carriers (holes) of the p-type material.
In the absence of an applied bias voltage, the net flow of charge in any one direction for a semiconductor diode is zero. 

➤ Reverse Bias Condition

If an external potential of V volts is applied across the p-n junction such that the positive terminal is connected to the n-type material and the negative terminal is connected to the p-type material, the number of uncovered positive ions in the depletion region of the n-type material will increase due to the large number of “free” electrons drawn to the positive potential of the applied voltage.  
For similar reasons, the number of uncovered negative ions will increase in the p-type material. The net effect, therefore, is a widening of the depletion region. This widening of the depletion region will establish too great a barrier for the majority carriers to overcome, effectively reducing the majority carrier flow to zero.
The number of minority carriers, however, that find themselves entering the depletion region will not change, resulting in minority-carrier flow. The current that exists under reverse bias conditions is called the reverse saturation current and is represented by 

I_s or I₀. 

Forward Bias Condition (V_D > 0V)

A forward-bias or “on” condition is established by applying the positive potential to the p-type material and the negative potential to the n-type material as shown in figure. Thus a semiconductor diode is forward-biased when the association p-type positive and n-type negative has been established.  
The application of a forward-bias potential V_D will “pressure” electrons in the n-type material and holes in the p-type material to recombine with the ions near the boundary and reduce the width of the depletion region. The resulting minority-carrier flow of electrons from the p-type material to the n-type material (and of holes from the n-type material to the p-type material) has not changed in magnitude (since the conduction level is controlled primarily by the limited number of impurities in the material), but the reduction in the width of the depletion region has resulted in a heavy majority flow across the junction. An electron in the n-type material now “sees” a reduced barrier at the junction due to the reduced depletion region and a strong attraction for the positive potential applied to the p-type material. As the applied bias increases in magnitude the depletion region will continue to decrease in width until a flood of electrons can pass through the junction, resulting in an exponential rise in current as shown in the forward-bias region of the characteristics.  

➤ Ideal Diode  

Before examining the construction and characteristics of an actual device, we first consider the ideal device, to provide a basis for comparison. The ideal diode is a two-terminal device having the symbol and characteristics shown in figure 2.4(a) and 2.4(b), respectively.  
Ideally, a diode will conduct current in the direction defined by the arrow in the symbol and act like an open circuit to any attempt to establish current in the opposite direction. In essence: The characteristics of an ideal diode are those of a switch that can conduct current in only one direction.  

The ideal diode, therefore, is a short circuit in the region of conduction and is an open circuit in the region of non conduction.  

Figure : (a) Conduction and (b) non-conduction states of the ideal diode as determined by the applied bias.

➤ Diode Characteristics (V_γ = 0.7V for Si and V_γ =0.3V for Ge)

It is clear from the characteristics of figure that to forward bias the diode minimum voltage of V_γ is required. This voltage V_γ is called cut-in voltage of the diode. The closer the upward swing is to the vertical axis, the more “ideal” the device. However, the other characteristics of silicon as compared to germanium still make it the choice in the majority of commercially available units.  

➤ Diode Equation 

 where I_s = reverse saturation current,
V_T = kT/e is volt equivalent of temperature and η = 1 for Ge and η = 2 for Si devices.
Note: The reverse saturation current in a germanium diode is normally larger by a factor of about 1000 than the reverse saturation current in a silicon diode of comparable ratings. 

I_s is in the range of μA for a Ge diode and nA for a silicon diode at room temperature. 

➤ Breakdown Diodes 

Diodes which are designed with adequate power-dissipation capabilities to operate in the breakdown region may be employed as voltage-reference or constant-voltage devices. Such diodes are known as avalanche, breakdown or Zener diodes. They are used characteristically in the manner indicated in the figure.

Figure: (a) Zener diode as voltage regulator (b) Zener charachteristics.

The source V and resistor R are selected so that initially, the diode is operating in the breakdown region. Here the diode voltage, which is also the voltage across the load R_L, is V_Z, and the diode current is I_Z. The diode will now regulate the load voltage against variations in load current and against variations in supply V, because in the break-down region only small changes in diode voltage produce large changes in diode current. Moreover, as load current or supply voltage changes, the diode current will accommodate itself to these changes to maintain a nearly constant load voltage. The diode will continue to regulate until the circuit operation requires the diode current to fall to I_ZK, in the neighborhood of the knee of the diode volt-ampere curve. The upper limit on diode current is determined by the power dissipation rating of the diode.   

➤ The Temperature Dependence of the V-I Characteristics 

The volt-ampere relationship contains the temperature implicitly in the two symbols V_T and I_s. If the temperature is increased at a fixed voltage, the current increases. However if we now reduce V, then I may be brought back to its previous value. It is found that for either silicon or germanium (at room temperature)  in order to maintain a constant value of I. It should be noted that  decreases with increasing T.  

Diode Resistances 

➤ DC or Static Resistance
The application of a dc voltage to a circuit containing a semiconductor diode will result in an operating point on the characteristic curve that will not change with time. The resistance of the diode at the operating point can be found simply by finding the corresponding levels of V_D and I_D as shown in figure and applying the following equation:
R_D = V_D/I_D
The dc resistance levels at the knee and below will be greater than the resistance levels obtained for the vertical rise section of the characteristics. The resistance levels in the reverse-bias region will naturally be quite high. Since ohmmeters typically employ a relatively constant current source, the resistance determined will be at a preset current level (typically, a few milliamperes).

Figure : Determining the dc resistance of a diode at a particular operating point.

➤ AC or Dynamic Resistance  

The dc resistance of a diode is independent of the shape of the characteristic in the region surrounding the point of interest. If a sinusoidal rather than dc input is applied, the situation will change completely. The varying input will move the instantaneous operating point up and down a region of the characteristics and thus defines a specific change in current and voltage as shown in figure (a). With no applied varying signal, the point of operation would be the Q-point appearing on figure determined by the applied dc levels. The designation Q-point is derived from the word quiescent which means “still or unvarying.”

Figure : (a) Defining ac Resistance. (b) Determining the ac Resistance at a Q-point.

A straight line drawn tangent to the curve through the Q-point as shown in figure (b) will define a particular change in voltage and current that can be used to determine the ac or dynamic resistance for this region of the diode characteristics. An effort should be made to keep the change in voltage and current as small as possible and equidistant to either side of the Q-point. In equation form rd = ΔV_d/ΔI_d where ∆ signifies a finite change in the quantity.
For small-signal operation the dynamic resistance r is an important parameter and is defined as the reciprocal of the slope of the volt ampere characteristic r = dV/dI
The dynamic resistance is not a constant, but depends upon the operating voltage.  
For a semiconductor diode, the dynamic conductance g ≡ 1/r

At room temperature, for η = 1, r = 26/I, where I is in mA and r is in Ω. For a forward  current of 26 mA the dynamic resistance is 1Ω.  

Diode Capacitances 

➤ Space-Charge or Transition Capacitance  

 A reverse bias causes majority carriers to move away from the junction, thereby uncovering more immobile charges. Hence the thickness of the space charge layer at the junction increases with reverse voltage. The increased in uncovered charge with applied voltage may be considered a capacitive effect. We may define an incremental capacitance C_T by: C_T = |dQ/dV|  where dQ is the increase in charge caused by a change dV in voltage. It follows from this definition that a change in voltage dV in a time dt will result in a  current i = dQ/dt given by  i = C_T(dV/dt) where C_T is not a constant, but depends upon the  magnitude of the reverse voltage. 

➤ Diffusion Capacitance  
For a forward bias a capacitance which is much larger than the transition capacitance lies in the injected charge stored near the junction outside the transition region. It is convenient to introduce an incremental capacitance, defined as the rate of change of injected charge with voltage, called the diffusion or storage, capacitance C_D.
Charge control description of a diode
If the bias is in the forward direction, the potential barrier at the junction is lowered and holes from the p-side enter the n- side. Similarly electrons from the n-side move into the p-side. This process of minority-carrier injection has been discussed earlier. The excess hole density falls off exponentially with distance.
Assume that one side of the diode, say the p material, is so heavily doped in comparison with the n side that the current I is carried across the junction entirely by holes moving from the p to the n side or I =I_pn (0). The excess minority charge Q will then exist only on the n side.  
Now I = Q/τ, where τ = τ_p = mean life for holes.  
The above equation states that the diode current (which consists of holes crossing the junction from the p to the n side) is proportional to the stored charge Q of excess minority carriers. The factor of proportionality is the reciprocal of the decay time constant (the mean lifetimeτ) of the minority carriers. Thus in the steady state, the current I supplies minority carriers at the rate at which these carriers are disappearing because of the process of recombination. 

Static Derivation of C_D
Since, I = Q/τ and
where g = dI/dV is the diode incremental conductance and r = 1/g is the diode incremental  resistance.
Thus

We see that the diffusion capacitance is proportional to the current I. In the above derivation we have assumed that the diode current I is due to holes only. If this assumption is not satisfied then above equation gives the diffusion capacitance  due 

holes only and a similar expression can be obtained for the diffusion capacitance  due 

to electrons. The total diffusion capacitance can then be obtained as the sum of and
Note: For a reverse bias, g is very small and C_D may be neglected compared with C_T.   For a forward current, on the other hand, C_D is usually much larger than C_T.
Despite the large value of C_D, the time constant rC_D may not be excessive because the dynamic forward resistance r = 1/g is small. Thus rC_D = τ. Hence, the diode time constant equals the mean lifetime of minority carriers, which lies in the range of nanoseconds (ns) to hundreds of microseconds(μs).  

Load Line Analysis 

The applied load will normally have an important impact on the point or region of operation of a device. If the analysis is performed in a graphical manner, a line can be drawn on the characteristics of the device that represents the applied load. The intersection of the load line with the characteristics will determine the point of operation of the system. Such an analysis is, for obvious reasons, called load-line analysis.  
Consider the network of figure 2.10(a) employing a diode having the characteristics of figure (b). Note in figure (a) that the “pressure” established by the battery is to establish a current through the series circuit in the clockwise direction. The fact that this current and the defined direction of conduction of the diode are a “match” reveals that the diode is in the “on” state and conduction has been established. The resulting polarity across the diode will be as shown in figure (a) and the first quadrant (VD and ID positive) of figure  (b) will be the region of interest – the forward-bias region.  

Applying Kirchhoff’s voltage law to the series circuit of figure (a) will result in  

-E + V_D + V_R = 0 ⇒ E = V_D + V_R
⇒ E = V_D + I_DR
The two variables of above equation (V_D and I_D) are the same as the diode axis variables of figure (a). This similarity permits a plotting of the equation on the same characteristics of figure (b).  
The intersections of the load line on the characteristics can easily be determined if one simply employs the fact that anywhere on the horizontal axis I_D = 0A and anywhere on the vertical axis V_D = 0 V.  

If we set V_D = 0V in equation E = V_D + I_DR and solve for I_D, we have the magnitude of 

I_D on the vertical axis. Thus E =V_D+ I_DR = 0V + I_DR and

If we set I_D = 0A in equation E = V_D + I_DR and solve for V_D, we have the magnitude of 

V_D on the horizontal axis. Thus E = V_D + ( 0A) R and V_D =
A straight line drawn between the two points will define the load line as depicted in figure . Change the level of R (the load) and the intersection on the vertical axis will change. The result will be a change in the slope of the load line and a different point of intersection between the load line and the device characteristics.
We now have a load line defined by the network and a characteristics curve defined by the device. The point of intersection between the two is the point of operation for this circuit. By simply drawing a line down to the horizontal axis the diode voltage  can be determined, whereas a horizontal line from the point of intersection to the vertical axis will provide the level of  . The current I_D is actually the current through the entire series configuration of figure (a). The point of operation is usually called the quiescent point (abbreviated “Q-point”) to reflect its “still, unmoving” qualities as defined by a dc network.
The solution obtained at the intersection of the two curves is the same that would be obtained by a simultaneous mathematical solution of equations E = V_D + I_DR and

Series Diode Configurations with DC Inputs 

In this section the approximate model is utilized to investigate a number of series diode configurations with dc inputs. The procedure described can, in fact, be applied to networks with any number of diodes in a variety of configurations.  
For each configuration the state of each diode must first be determined. Which diodes are “on” and which are “off”? Once determined, the appropriate equivalent can be substituted and the remaining parameters of the network determined.  
In general, a diode is in the “on” state if the current established by the applied sources is such that its direction matches that of the arrow in the diode symbol, and V_D ≥ 0.7 V for silicon and V_D ≥ 0.3 V for germanium.  
For each configuration, mentally replace the diodes with resistive elements and note the resulting direction as established by the applied voltages (“pressure”). If the resulting direction is a “match” with the arrow in the diode symbol, conduction above is, of course, contingent on the supply having a voltage greater than the “turn-on” voltage ( V_γ ) of each diode.
If a diode is in the “on” state, one can either place a 0.7 V drop across the element, or the network can be redrawn with the V_γ equivalent circuit. In time the preference will probably simply be to include the 0.7 V drop across each “on” diode and draw a line through each diode in the “off” or open state. Initially, however, the substitution method will be utilized to ensure that the proper voltage and current levels are determined.  
The series circuit of figure (a) will be used to demonstrate the approach described in the paragraphs above. The state of the diode is first determined by mentally replacing the diode with a resistive element as shown in figure (b). The resulting direction of I is a match with the arrow in the diode symbol and since E > V_γ the diode is in the “on” state. The network is then redrawn as shown in figure (c) with the appropriate equivalent model for the forward-biased silicon diode. Note for future reference that the polarity of V_D is the same as would result if in fact the diode were a resistive element.  

The resulting voltage and current levels are the following.  
V_D = V_γ, V_R = E-V_γ and I_D = I_R = (V_R/R).
In figure (a) the diode of figure (a) has been reversed. Mentally replacing the diode with a resistive element as shown in figure (b) will reveal that the resulting current direction does not match the arrow in the diode symbol. The diode is in the “off” state, resulting in the equivalent circuit of figure (c). Due to the open circuit, the diode current is 0 A and the voltage across the resistor R is the following:  
V_R = I_RR = I_DR = 0V

Figure (c): Substituting the equivalent model for the “off” diode of figure (a).

The fact that V_R = 0V will establish E volts across the open circuit as defined by Kirchhoff’s voltage law. Always keep in mind that under any circumstances–dc, ac instantaneous values, pulses, and so on – Kirchhoff’s voltage law must be satisfied!  

Example: For the series diode configuration of figure shown below, determine VD, VR, and ID. 

Since the applied voltage establishes a current in the clockwise direction to match the arrow of the symbol and the diode is in the “on” state.

V_D = 0.7 V, V_R = E – V_D = 8 V – 0.7 V = 7.3 V

Example: Repeat above example with the diode reversed.  

Removing the diode, we find that the direction of I is opposite to the arrow in the diode symbol and the diode equivalent is the open circuit no matter which model is employed. The result is the network of figure shown below, where ID = 0 A due to the open circuit. Since V_R = I_RR, VR = (0)R = 0 V.

 Applying Kirchhoff’s voltage law around the closed loop yields
-E +V_D + V_R = 0  
and V_D = E – V_R = E – 0 = E = 8 V

Example: For the series diode configuration of figure shown below, determine V_D, V_R, and I_D.

Although the “pressure” establishes a current  with the same direction as the arrow symbol the level of  applied voltage is insufficient to turn the silicon diode  “on”. The resulting voltage and current levels are therefore  the following:  

I_D = 0 A, V_R = I_RR = I_DR = (0 A) 1.2 kΩ = 0 V and V_D = E = 0.5 V

Example: Determine V₀ and I_D for the series circuit of figure shown below.  

The resulting current has the same direction as the arrowheads of the symbols of both diodes, and the network of figure shown below results because  E = 12V> ( 0.7 V + 0.3 V) = 1 V .Note the redrawn supply of 12 V and the polarity of V₀ across the 5.6 kΩ resistor. The resulting voltage  

Example: Determine I, V₁, V₂ and V₀ for the series dc configuration of figure shown below.   

The sources are drawn and the current direction indicated as shown in figure below. Note that the “on” state is noted simply by the additional V_D= 0.7 V on the figure. This eliminates the need to redraw the network and avoids any confusion that may result from the appearance of another source.

 The resulting current through the circuit is,  

and the voltages are V₁ = IR₁ = (2.07 mA) (4.7 kΩ) = 9.73 V
V₂ = IR₂ = (2.07 mA) (2.2 kΩ) = 4.55 V
Applying Kirchhoff’s voltage law to the output section in the clockwise direction will result in  +E₂ -V₂ +V₀ = 0 and    V₀ = V₂ – E₂ = 4.55 V – 5 V = - 0.45 V.
The minus sign indicates that V₀ has a polarity opposite to that appearing in figure.  

Parallel and Series–Parallel Configurations  

The methods applied in series configurations can be extended to the analysis of parallel and series-parallel configurations. For each area of application, simply match the sequential series of steps applied to series diode configurations.   

Example: Determine V₀, I₁, I_D1 and I_D2 for the parallel diode configuration as shown in figure.  

For the applied voltage the “pressure” of the source is to establish a current through each diode in the same direction as shown in figure below. Since the resulting current direction matches that of the arrow in each diode symbol and the applied voltage is greater than 0.7 V, both diodes are in the “on” state. The voltage across parallel elements is always the same and V₀ = 0.7 V.

The current

Assuming diodes of similar characteristics,

Example: Determine the current I for the network shown in figure below.

Redrawing the network as shown in figure reveals that the resulting current direction is such as to turn on diode D₁ and turn off diode D₂. The resulting current I is then  

Rectifiers

➤ Half-Wave Rectification
This circuit will generate a waveform v_o that will have an average value of particular use in the ac-to-dc conversion process.  

During the interval t = 0 → T/2 the polarity of the applied voltage is such as to establish “pressure” in the direction indicated and turn on the diode with the polarity appearing above the diode. Substituting the short-circuit equivalence for the ideal diode will result in the equivalent circuit shown in figure, where it is fairly obvious that the output signal is an exact replica of the applied signal. The two terminals defining the output voltage are connected directly to the applied signal via the short-circuit equivalence of the diode.

For the period t = T/2 → T, the polarity of input v_i is shown in figure and the resulting polarity across the ideal diode produces an “off” state with an open circuit equivalent. The result is the absence of a path for charge to flow and v₀ = 0V for the period T/2 → T .  

The process of removing one-half the input signal to establish a dc level is aptly called half-wave rectification.  
The input v_i and the output v₀ were sketched together in figure for comparison purposes. The output signal v₀ now has a net positive area above the axis over a full period and an average value determined by

The process of removing one-half the input signal to establish a dc level is aptly called half-wave rectification.

NOTE: The effect of using a silicon diode with V_γ = 0.7V is demonstrated in figure for the forward-bias region. The applied signal must now be at least 0.7V before the diode can turn “on.” For levels of v_i less than 0.7V the diode is still in an open-circuit state and v_o = 0V . When conducting, the difference between v_o and v_i is a fixed level of  V_γ = 0.7V and v₀ =v_i−V_γ . The net effect is a reduction in area above the axis, which naturally reduces the resulting dc voltage level. For situations where V_m >>V_γ equation given below can be applied to determine the average value with a relatively high level of accuracy.

Peak Inverse Voltage (PIV) or Peak Reverse Voltage (PRV)  

It is the voltage rating that must not be exceeded in the reverse-bias region. The required PIV rating for the half-wave rectifier can be determined from figure, which displays the reverse-biased diode with maximum applied voltage. Applying Kirchhoff’s voltage law, it is fairly obvious that the PIV rating of the diode must equal or exceed the peak value of the applied voltage. Therefore, PIV rating ≥ V_m

Figure : Determining the required PIV rating for the half-wave rectifier.

➤ Full Wave Rectification  

(i) Bridge Network  

The dc level obtained from a sinusoidal input can be improved 100% using a process called full-wave rectification. The most familiar network for performing such function appears in figure with its four diodes in a bridge configuration.  

During period t = 0→T/2 the polarity of the input is shown in figure. The resulting polarities across the ideal diodes are shown to reveal that D₂ and D₃  are conducting while D₁ and D₄  are in the “off” state.

The net result is the configuration of figure, with its indicated current and polarity across R. Since the diodes are ideal the load voltage v₀ =v_i .

For the negative region of the input the conducting diodes are D₁  and D₄ , resulting in the configuration of figure. The important result is that the polarity across the load resistor R is the same as during positive half cycle.  
 

Figure : Conduction path for the negative region of v_i.

Over one full cycle the input and output voltages will appear as shown in figure.   

Figure : Input and output waveforms for a full-wave rectifier.

Since the area above the axis for one full cycle is now twice that obtained for half-wave system, the dc level has also been doubled and  

NOTE: If silicon rather than ideal diodes are employed as shown in figure, an application of Kirchhoff’s voltage law around the conduction path would result in  
− v_i + V_γ + v_o + V_γ = 0 And  v_o = v_i − 2V_γ
The peak value of the output voltage v₀ is therefore  

Figure : Determining V_omax for silicon diodes in the bridge configuration.

For situations where V_m >> 2V_γ equation given below can be applied to determine the average value with a relatively high level of accuracy.    
V_dc ≌  0.636(V_m − 2V_γ)

PIV 

The required PIV of each diode (ideal) can be determined from figure obtained at the peak of the positive region of the input signal. For the indicated loop the maximum voltage across R is V_m and the PIV rating is defined by PIV ≥ V_m

Figure : Determining the required PIV rating for the bridge configurations.

(ii) Center-Tapped transformer 

A second popular full-wave rectifier appears in figure with only two diodes but requiring a center-tapped (CT) transformer to establish the input signals across each section of the secondary of the transformer.  

Figure : Centre-tapped transformer full-wave rectifier.

During the positive portion of v_i applied to the primary of the transformer, the network will appear as shown in figure. D₁ assumes the short-circuit equivalent and D₂  the open circuit equivalent as detrmined by the secondary voltages and the resulting current directions. The output voltage v₀ appears as shown in figure.  

During the negative portion of the input the network appears as shown in figure, reversing the roles of the diodes but maintaining the same polarity for the voltage across the load resistor R. The net effect is the same output as that appearing in positive half cycle with the same dc levels.

PIV : The network of figure will help us determine the net PIV for each diode for this full-wave rectifier. Inserting the maximum voltage for the secondary voltage and V_m as established by the adjoining loop will result in  

PIV = V_secondary + V_R  = V_m + V_m and PIV ≥ 2V_m .

Clippers 

There are a variety of diode networks called clippers that have the ability to “clip” off a portion of the input signal without distorting the remaining part of the alternating waveform. The half-wave rectifier is an example of the simplest form of diode clipper– one resistor and diode. Depending on the orientation of the diode, the positive or negative region of the input signal is “clipped” off.  

➤ Series Clippers (Positive and Negative) 

The response of the series configuration of figure (a) to a variety of alternating waveforms is provided in figure (b). Although first introduced as a half-wave rectifier (for sinusoidal waveforms), there are no boundaries on the type of signals that can be applied to a clipper.

The addition of dc supply such as shown in figure can have a pronounced effect on the output of a clipper. Our initial discussion will be limited to ideal diodes and the effect of V_γ will be discussed later.  

There is no general procedure for analyzing above networks, but there are a few thoughts to keep in mind before analyzing these circuits.  

• Make a mental sketch of the response of the network based on the direction of the    diode and the applied voltage levels.

The direction of the diode suggests that the signal vi must be positive to turn it on. The dc supply further requires that the voltage vi be greater than V volts to turn the diode on. The negative region of the input signal is “pressuring” the diode into the “off” state, supported further by the dc supply. In general, therefore, we can be quite sure that the diode is an open circuit (“off” state) for the negative region of the input signal. 

• Determine the applied voltage (transition voltage) that will cause change in state for the diode.

For the ideal diode the transition between states will occur at the point on the characteristic where v_d = 0V and i_d = 0A. Applying the condition i_d = 0A at v_d = 0 will result in the configuration of figure, where it is recognized that the level of v_i that will cause a transition in state is: v_i =V.  

For an input voltage greater than V volts the diode is in the short-circuit state, while for input voltage less than V volts it is in the open-circuit or “off” state. 

• Be continually aware of the defined terminals and polarity of v_o.  

When the diode is in the short-circuit state such as shown in figure, the output voltage v_o can be determined by applying Kirchhoff’s voltage law in the clockwise direction. 

• It can be helpful to sketch the input signal above the output and determine the output at instantaneous values of the input.  

It is then possible that the output voltage can be sketched from the resulting data points of v_o as demonstrated in figure.

Keep in mind that at an instantaneous value of v_i the input can be treated as a dc supply of that value and the corresponding dc value (the instantaneous value) of the output determined. For instance, at v_i=V_m the network to be analyzed appears in figure.

For V_m >V the diode is in the short-circuit state and v_o =V_m − V . At v_i =V the diodes change state and at v_i =−V_m ,  v_o = 0V and the complete curve for v_o can be sketched as shown in figure.

Example: Determine the output waveform for the network shown in figure below.

 The diode will be in “on” state for the positive region of v_i , especially when we note the aiding effect of V= 5V. The network will then appear as shown in figure (a) and v₀ = v_i + 5V. Substituting i_d = 0 at v_d = 0 for the transition levels, we obtain the network of figure (b) and v_i = -5V. 

For v_i more negative than − 5V the diode will enter its open-circuit state, while for voltages more positive than − 5V the diode is in the short-circuit state. The input and output voltage appear in figure shown below.  

Example: Repeat above example for the square-wave input shown in figure below.  

For v_i = 20V(0→T/2) the network of figure (a) will result. The diode is in the short-circuit state and v₀ = 20V+5V = 25V. For v_i = -10V the network of figure (b) will result, placing the diode in the “off” state and v₀ = i_RR = 0 x R = 0V. The resulting output voltage appears in figure (c). 

➤ Parallel Clippers (Positive and Negative)

The network of figure is the simplest of parallel diode configurations with the output for the same inputs. The analysis of parallel configurations is very similar to that applied to series configurations, as demonstrated in the next example.   

Example: Determine v₀ for the network of figure shown below.  

The polarity of the dc supply and the direction of the diode strongly suggest that the diode will be in the “on” state for the negative region of the input signal. For this region the network will appear as shown in figure below where the defined terminals for v₀ require that v₀ = V = 4V.

The transition state can be determined from figure shown below, where the condition i_d = 0A at v_d = 0V has been imposed. The result is v_i (transition) = V = 4V.

Since the dc supply is obviously “pressuring” the diode to stay in the short-circuit state, the input voltage must be greater than 4 V for the diode to be in the “off” state. Any input voltage less than 4V will result in a short-circuited diode.
For the open-circuit state the network will appear as shown in figure below, where v₀ = v_i. Completing the sketch of v₀ results in the waveform of figure shown below.   

To examine the effect of V_γ on the output voltage, the next example will specify a silicon diode rather than an ideal diode equivalent.  

Example: Repeat above example using a silicon diode with V_γ = 0.7 V.  

The transition voltage can first be determined by applying the condition i_d = 0 A at v_d = 0.7V and obtaining the network of figure shown below. Applying Kirchhoff’s voltage law around the output loop in the clockwise direction, we find that  − v_i − V_γ + V = 0

and v_i = V - V_γ = 4 - 0.7 = 3.3V
v_R = i_dR = 0 x R = 0V

For input voltages greater than 3.3V, the diode will be an open circuit and v₀ = v_i . For input voltages of less than 3.3 V, the diode will be in the “on” state and the network of figure shown below results, where v₀ = 3.3V.
Note that the only effect of V_γ was to drop the transition level to 3.3 V from 4 V.  
There is no question that including the effects of V_γ was to drop the transition level to 3.3 V from 4V.  

➤ Summary Clippers Networks  

A variety of series and parallel clippers with the resulting output for the sinusoidal input are provided in figures shown below. In particular, note the response of the last configuration, with its ability to clip off a positive and a negative section as determined by the magnitude of the dc supplies.  

➤ Simple Series Clippers (Ideal Diodes)  

Positive: 

Negative:  

➤ Biased Series Clippers (Ideal Diodes)  

Positive: 

Negative  

➤ Simple Parallel Clippers (Ideal Diodes) 

Positive:  

Negative:  

➤ Biased Parallel Clippers (Ideal Diodes)

Negative:  

Miscellaneous

Clampers 

The clamping network is one that will “clamp” a signal to a different dc level. The network must have a capacitor, a diode, and a resistive element, but it can also employ an independent dc supply to introduce an additional shift. The magnitude of R and C must be chosen such that the time constant τ = RC is large enough to ensure that the voltage across the capacitor does not discharge significantly during the interval the diode is    non-conducting. Throughout the analysis we will assume that for all practical purposes the capacitor will fully charge or discharge in five time constants.
The network of figure will clamp the input signal to the zero level (for ideal diodes).  

During the interval 0→T/2 the network will appear as shown in figure, with the diode in the “on” state effectively “shorting out” the effect of resistor R. The resulting RC time constant is so small (R is determined by the inherent resistance of the network) that the capacitor will charge to V volts very quickly.  

During this interval the output voltage is directly across the short circuit and v_o = 0 V.
When the input switches to –V state, the network will appear as shown in figure 2.41, with the open-circuit equivalent for the diode determined by the applied signal and stored voltage across the capacitor-both “pressuring” current through the diode from cathode to anode.  

Now that R is back in the network the time constant determined by the RC product is sufficiently large to establish a discharge period 5τ much greater than the period T/2→T and it can be assumed on an approximate basis that the capacitor holds onto all its charge and therefore voltage (since V = Q/C) during this period.  
Applying Kirchhoff’s voltage law around the input loop will result in  + V+ V+ v_o = 0 and  v_o = – 2V.
The negative sign resulting from the fact that the polarity of 2V is opposite to the polarity defined for v_o. The resulting output waveform appears in figure with the input signal. The output signal is clamped to 0 V for the interval 0 to T/2 but maintains the same total swing (2V) as the input.   

For a clamping network:  
The total swing of the output is equal to the total swing of the input signal.  
This fact is an excellent checking tool for the result obtained.  

In general, the following steps may be helpful when analyzing clamping networks:  

1. Start the analysis of clamping networks by considering that part of the input signal that will forward bias the diode.
2. During the period that the diode is in the “on” state, assume that the capacitor will charge up instantaneously to a voltage level determined by the network.  
3. Assume that during the period when the diode is in the “off” state the capacitor will hold on to its established voltage level.  
4. Throughout the analysis maintain a continual awareness of the location and reference polarity for v_o to ensure that the proper levels for v_o are obtained.  
5. Keep in mind the general rule that the total swing of the total output must match the swing of the input signal.  

Example: Determine v_o for the network of figure (a) for the input indicated.  

Note that the frequency is 1000 Hz, resulting in a period of 1 ms and an interval of 0.5 ms between levels. The analysis will begin with the period t₁→ t₂ of the input signal since the diode is in it short-circuit state as recommended by comment 1.
For this interval the network will appear as shown in figure (b). The output is across R, but it is also directly across the 5V battery if you follow the direct connection between the defined terminals for v_o and the battery terminals. The result is v_o = 5V for this interval.  
Applying Kirchhoff’s voltage law around the input loop will result in +20V-V_C +5V = 0 and V_C = 25 V.  

The capacitor will therefore, charge up to 25V, as stated in comment 2. In this case the resistor R is not shorted out by the diode but a Thevenin’s equivalent circuit of that portion of the network which includes the battery and the resistor will result in R_Th = 0 Ω with E_Th = V = 5 V.

For the period t₂ → t₃ the network will appear as shown in figure (c). The open-circuit equivalent for the diode will remove the 5V battery from having any effect on v_o, and applying Kirchhoff’s voltage law around the outside loop of the network will result in
-10 V - 25 V – v_o = 0  and v_o = 35 V.   

The time constant of the discharging network of figure (c) is determined by the product RC and has the magnitude: τ = RC = (100 kΩ) (0.1 μF) = 0.01 s = 10 ms 

The total discharge time is therefore 5τ = 5 (10 ms) = 50 ms.  
Since the interval t₂ → t₃ will only last for 0.5 ms, it certainly a good approximation that the capacitor will hold its voltage during the discharge period between pulses of the input signals. The resulting output appears in figure (d) with the input signal. Note that the output swing of 30 V matches the input swing as noted in step 5.  

Example: Repeat above example using a silicon diode with V_γ = 0.7 V.  

For the short-circuit state the network now takes form of figure (a) and v_o can be determined by Kirchhoff’s voltage law in the output section.  

Figure (a): Determining v_o and V_C with the diode in the “on” state

-5V+0.7 V+ v_o = 0  
and  v_o = 5V – 0.7 V = 4.3 V

For the input section Kirchhoff’s voltage law will result in
+20V-V_C –0.7V+5V = 0
and V_C = 25 V – 0.7 V = 24.3 V.  

For the period t₂ → t₃ the network will now appear as in figure (b) with the only change being the voltage across the capacitor. Applying Kirchhoff’s voltage law yields
-10V-24.3 V+ v_o = 0 and  v_o = 34.3 V.
The resulting output appears in figure (c) verifying the statements that the input and output swings are the same.

➤ Summary Clamping Networks

Zener Diode 

The analysis of networks employing Zener diodes is quite similar to that applied to the analysis of semiconductor diodes. First the state of the diode must be determined followed by a substitution of the appropriate model and a determination of the other unknown quantities of the network. The Zener model to be employed for the “on” state and for the “off” state as defined by a voltage less than V_Z but greater than 0V with the polarity indicated as shown in figure.

Figure : Zener diode equivalents for the (a) “on” and (b) “off” states.

➤ Case-I (V_i and R_L fixed) 

The simplest of Zener diode networks appears as shown in figure.

Figure: Basic Zener regulator.

The applied dc voltage is fixed, as is the load resistor. The analysis can fundamentally be broken down into two steps.  
1. Determine the state of the Zener diode by removing it from the network and calculating the voltage across the resulting open circuit.
Open circuit voltage
If V ≥V_Z , the Zener is “on” and if V <V_Z  , the Zener is “off.”

Figure : Determining the state of the Zener diode.  

2. Substitute the appropriate equivalent circuit and solve for the desired unknowns. 

Figure : Substituting the Zener equivalent for the “on” situation.  

When the Zener is “on” then V_L =V_Z and I_R = I_Z + I_L ⇒ I_Z = I_R − I_L

where
Power dissipated by the Zener diode P_Z =V_Z I_Z ≤ P_ZM .

Note: If the Zener diode is in the “on” state, the voltage across the diode is not V volts. When the system is turned on the Zener diode will turn “on” as soon as the voltage across the Zener diode is volts V_Z . It will then “lock in” at this level and never reach the higher 

level of V volts.
Zener diodes are most frequently used in regulator network or a reference voltage. A simple regulator designed to maintain a fixed voltage across the load RL . For values of applied voltage greater than required to turn the Zener diode “on,” the voltage across the load will be maintained at volts V_Z. If the Zener diode is employed as a reference voltage, it will provide a level for comparison against other voltages. 

Example: (a) For the Zener diode network of figure (a), determine V_L ,V_R, I_Z and P_Z. (b) Repeat part (a) with R_L = 3 kΩ .  

(a) Following the suggested procedure the network is redrawn as shown in figure (b).
Open circuit voltage
 

Since V = 8.73V is less than V_Z = 10V the diode is in the “off” state. Substituting the open-circuit equivalent we will find that  
V_L =V= 8.73 V
V_R =V_i− V_L = 16 V − 8.73 V = 7.27 V
I_Z = 0A and P_Z =V_Z I_Z= 0 W .
(b) Open circuit voltage  

Since V = 12V is greater than V_Z = 10V , the diode is in the “on” state and the network of figure (c) will result. 

V_L =V_Z= 10 V and V_R =V_i− V_L = 6 V

with
and
I_Z = I_R−I_L = 6 mA −3.33 mA = 2.67 mA . The power dissipated, P_Z =V_Z I_Z= 26.7 mW which is less than the specified 30 P_ZM =mW .

➤ Case-II ( fixed V_i and variable R_L)

Due to the offset voltage V_Z , there is a specific range of resistor values (and therefore load current) which will ensure that the Zener is in the “on” state. Too small a load resistance R_L will result in a voltage V_L across the load resistor less than V_Z and the Zener device will be in the “off” state.
To determine the minimum load resistance that will turn the Zener diode on, simply calculate the value of R_L that will result in a load voltage V_L =V_Z.
That is,   Solving for R_L we have
Any load resistance value greater than the R_L obtained from above equation will ensure that the Zener diode is in the “on” sate and the diode can be replaced by its V_Z source equivalent.  
This condition establishes the minimum R_L , but in turn specifies the maximum I_L as  

Once the diode is in the “on” state, the voltage across R remains fixed at  V_R = V_i-V_Z and I_R  remains fixed at I_R = V_R/R
The Zener current I_Z = I_R−I_L resulting in a minimum I_Z when I_L is a maximum and a maximum I_Z when I_L is a minimum value since I_R is constant.
Since I_Z is limited to I_ZM as provided on the data sheet, it does affect the range of R_L and therefore I_L. Substituting I_ZM for I_Z establishes the minimum I_L as    and the maximum load resistance as

Example: (a) For the network of figure shown determines the range of R_L and I_L that will result in R_LV being maintained at 10 V.  
(b) Determine the maximum voltage rating of the diode.  

(a) To determine the value of RL that will turn the Zener diode on, apply equation    

The voltage across the resistor R is then determined by equation
V_R =V_i− V_Z = 50 V − 10 V = 40 V and
The minimum level of I_L is then determined by equation

with

➤ Case-III ( fixed R_L and variable V_i)
For fixed values of R_L , the voltage V_i must be sufficiently large to turn the Zener diode on. The minimum turn-on voltage  is determined by  

The maximum value of V_i is limited by the maximum Zener current I_ZM. Since I_ZM = I_R−I_L,
Since I_L is fixed at V_Z /R_L and I_ZM is the maximum value of I_Z, the maximum V_i is defined by

Example: Determine the range of values of V_i that will maintain the Zener diode in the “on” state.  

 (76.67mA) (0.22 kΩ) + 20V =16.87V + 20V = 36.87V

➤ Zener as a Reference Levels

Two or more reference levels can be established by placing Zener diodes in series as shown in figure. As long as V_i is greater than the sum of  both diodes will be in the “on” state and the three reference voltages will be available.  

Two back-to-back Zener can also be used as an ac regulator as shown in figure. For the sinusoidal signal v_i the circuit will appear as shown in figure at the instant v_i = 10V.  

The region of operation for each diode is indicated in the adjoining figure. Note that Z₁ is in a low-impedance region, while the impedance of Z₂ is quite large, corresponding with the open-circuit representation. The result is that v_o = v_i when v_i = 10V . The input and output will continue to duplicate each other until v_i reaches 20 V. Z₂ will then “turn on” (as a Zener diode) while Z₁ will be in a region of conduction with a resistance level sufficiently small compared to the series 5 kΩ resistor to be considered a short circuit. The resulting output for the full range of v_i is provided in figure. Note that the waveform is not purely sinusoidal, but its rms value is lower than that associated with a full 22 V peak signal.