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Page 1 1 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PIPELINING AND VECTOR PROCESSING Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors(refer book) Page 2 1 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PIPELINING AND VECTOR PROCESSING Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors(refer book) 2 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL PROCESSING Levels of Parallel Processing - Job or Program level - Task or Procedure level - Inter-Instruction level - Intra-Instruction level Execution of Concurrent Events in the computing process to achieve faster Computational Speed Parallel Processing Page 3 1 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PIPELINING AND VECTOR PROCESSING Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors(refer book) 2 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL PROCESSING Levels of Parallel Processing - Job or Program level - Task or Procedure level - Inter-Instruction level - Intra-Instruction level Execution of Concurrent Events in the computing process to achieve faster Computational Speed Parallel Processing 3 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL COMPUTERS Architectural Classification Number of Data Streams Number of Instruction Streams Single Multiple Single Multiple SISD SIMD MISD MIMD Parallel Processing – Flynn's classification » Based on the multiplicity of Instruction Streams and Data Streams » Instruction Stream Sequence of Instructions read from memory » Data Stream Operations performed on the data in the processor Page 4 1 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PIPELINING AND VECTOR PROCESSING Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors(refer book) 2 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL PROCESSING Levels of Parallel Processing - Job or Program level - Task or Procedure level - Inter-Instruction level - Intra-Instruction level Execution of Concurrent Events in the computing process to achieve faster Computational Speed Parallel Processing 3 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL COMPUTERS Architectural Classification Number of Data Streams Number of Instruction Streams Single Multiple Single Multiple SISD SIMD MISD MIMD Parallel Processing – Flynn's classification » Based on the multiplicity of Instruction Streams and Data Streams » Instruction Stream Sequence of Instructions read from memory » Data Stream Operations performed on the data in the processor 4 Pipelining and Vector Processing Computer Organization Computer Architectures Lab COMPUTER ARCHITECTURES FOR PARALLEL PROCESSING Von-Neuman based Dataflow Reduction SISD MISD SIMD MIMD Superscalar processors Superpipelined processors VLIW Nonexistence Array processors Systolic arrays Associative processors Shared-memory multiprocessors Bus based Crossbar switch based Multistage IN based Message-passing multicomputers Hypercube Mesh Reconfigurable Parallel Processing Page 5 1 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PIPELINING AND VECTOR PROCESSING Parallel Processing Pipelining Arithmetic Pipeline Instruction Pipeline RISC Pipeline Vector Processing Array Processors(refer book) 2 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL PROCESSING Levels of Parallel Processing - Job or Program level - Task or Procedure level - Inter-Instruction level - Intra-Instruction level Execution of Concurrent Events in the computing process to achieve faster Computational Speed Parallel Processing 3 Pipelining and Vector Processing Computer Organization Computer Architectures Lab PARALLEL COMPUTERS Architectural Classification Number of Data Streams Number of Instruction Streams Single Multiple Single Multiple SISD SIMD MISD MIMD Parallel Processing – Flynn's classification » Based on the multiplicity of Instruction Streams and Data Streams » Instruction Stream Sequence of Instructions read from memory » Data Stream Operations performed on the data in the processor 4 Pipelining and Vector Processing Computer Organization Computer Architectures Lab COMPUTER ARCHITECTURES FOR PARALLEL PROCESSING Von-Neuman based Dataflow Reduction SISD MISD SIMD MIMD Superscalar processors Superpipelined processors VLIW Nonexistence Array processors Systolic arrays Associative processors Shared-memory multiprocessors Bus based Crossbar switch based Multistage IN based Message-passing multicomputers Hypercube Mesh Reconfigurable Parallel Processing 5 Pipelining and Vector Processing Computer Organization Computer Architectures Lab SISD COMPUTER SYSTEMS Control Unit Processor Unit Memory Instruction stream Data stream Characteristics - Standard von Neumann machine - Instructions and data are stored in memory - One operation at a time Limitations Von Neumann bottleneck Maximum speed of the system is limited by the Memory Bandwidth (bits/sec or bytes/sec) - Limitation on Memory Bandwidth - Memory is shared by CPU and I/O Parallel ProcessingRead More
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FAQs on PPT: Pipelining & Vector Processing - Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE)
| 1. What is pipelining in computer architecture? |  |
Ans. Pipelining is a technique used in computer architecture to maximize instruction execution throughput. It involves breaking down the execution of instructions into smaller stages and allowing multiple instructions to overlap in execution. This improves the overall efficiency of the processor by reducing idle time and increasing instruction throughput.
| 2. How does pipelining work? | |
Ans. Pipelining works by dividing the execution of instructions into multiple stages, such as instruction fetch, decode, execute, memory access, and write back. Each stage performs a specific operation on the instruction, and multiple instructions are processed simultaneously in different stages. This allows for the overlapping of instructions, resulting in improved throughput and faster execution of programs.
| 3. What are the advantages of pipelining? | |
Ans. Pipelining offers several advantages in computer architecture. Firstly, it improves the overall performance of the processor by allowing multiple instructions to be executed simultaneously. Secondly, it reduces the latency of instruction execution, as each instruction spends less time in the pipeline. Finally, it increases the utilization of the processor, as idle time is minimized by overlapping instruction execution.
| 4. What are the limitations of pipelining? | |
Ans. Despite its advantages, pipelining has certain limitations. One limitation is the occurrence of hazards, such as data hazards, control hazards, and structural hazards. These hazards can lead to stalls or incorrect results in the pipeline. Another limitation is the increase in the complexity of the processor's control logic, which can make the design more challenging and costly. Additionally, branch instructions can disrupt the pipeline by introducing control hazards, requiring additional measures to handle them effectively.
| 5. How is vector processing different from pipelining? | |
Ans. Vector processing is a type of parallel processing that involves performing the same operation on multiple data elements simultaneously. It differs from pipelining, which focuses on breaking down the execution of instructions into smaller stages. Vector processing is specifically designed for tasks that involve large amounts of data and can provide significant performance improvements in applications such as scientific simulations, image processing, and data analytics.
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