PPT: Pipelining & Vector Processing Notes | Study Digital Electronics - Electronics and Communication Engineering (ECE)

 Page 1


1 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PIPELINING  AND  VECTOR  PROCESSING
 Parallel Processing
 Pipelining
 Arithmetic Pipeline
 Instruction Pipeline
 RISC Pipeline
 Vector Processing
 Array Processors(refer book)
Page 2


1 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PIPELINING  AND  VECTOR  PROCESSING
 Parallel Processing
 Pipelining
 Arithmetic Pipeline
 Instruction Pipeline
 RISC Pipeline
 Vector Processing
 Array Processors(refer book)
2 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  PROCESSING
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
Parallel Processing
Page 3


1 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PIPELINING  AND  VECTOR  PROCESSING
 Parallel Processing
 Pipelining
 Arithmetic Pipeline
 Instruction Pipeline
 RISC Pipeline
 Vector Processing
 Array Processors(refer book)
2 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  PROCESSING
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
Parallel Processing 3 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  COMPUTERS
Architectural Classification
Number of Data Streams
Number of
Instruction
Streams
Single
Multiple
Single Multiple
SISD SIMD
MISD MIMD
Parallel Processing
– Flynn's classification
» Based on the multiplicity of Instruction Streams and
Data Streams
» Instruction Stream
 Sequence of Instructions read from memory
» Data Stream
 Operations performed on the data in the processor
Page 4


1 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PIPELINING  AND  VECTOR  PROCESSING
 Parallel Processing
 Pipelining
 Arithmetic Pipeline
 Instruction Pipeline
 RISC Pipeline
 Vector Processing
 Array Processors(refer book)
2 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  PROCESSING
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
Parallel Processing 3 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  COMPUTERS
Architectural Classification
Number of Data Streams
Number of
Instruction
Streams
Single
Multiple
Single Multiple
SISD SIMD
MISD MIMD
Parallel Processing
– Flynn's classification
» Based on the multiplicity of Instruction Streams and
Data Streams
» Instruction Stream
 Sequence of Instructions read from memory
» Data Stream
 Operations performed on the data in the processor
4 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
COMPUTER  ARCHITECTURES  FOR  PARALLEL
PROCESSING
Von-Neuman
based
Dataflow
Reduction
SISD
MISD
SIMD
MIMD
Superscalar processors
Superpipelined processors
VLIW
Nonexistence
Array processors
Systolic arrays
Associative processors
Shared-memory multiprocessors
Bus based
Crossbar switch based
Multistage IN based
Message-passing multicomputers
Hypercube
Mesh
Reconfigurable
Parallel Processing
Page 5


1 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PIPELINING  AND  VECTOR  PROCESSING
 Parallel Processing
 Pipelining
 Arithmetic Pipeline
 Instruction Pipeline
 RISC Pipeline
 Vector Processing
 Array Processors(refer book)
2 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  PROCESSING
Levels of Parallel Processing
- Job or Program level
- Task or Procedure level
- Inter-Instruction level
- Intra-Instruction level
Execution of Concurrent Events in the computing
process to achieve faster Computational Speed
Parallel Processing 3 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
PARALLEL  COMPUTERS
Architectural Classification
Number of Data Streams
Number of
Instruction
Streams
Single
Multiple
Single Multiple
SISD SIMD
MISD MIMD
Parallel Processing
– Flynn's classification
» Based on the multiplicity of Instruction Streams and
Data Streams
» Instruction Stream
 Sequence of Instructions read from memory
» Data Stream
 Operations performed on the data in the processor
4 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
COMPUTER  ARCHITECTURES  FOR  PARALLEL
PROCESSING
Von-Neuman
based
Dataflow
Reduction
SISD
MISD
SIMD
MIMD
Superscalar processors
Superpipelined processors
VLIW
Nonexistence
Array processors
Systolic arrays
Associative processors
Shared-memory multiprocessors
Bus based
Crossbar switch based
Multistage IN based
Message-passing multicomputers
Hypercube
Mesh
Reconfigurable
Parallel Processing 5 Pipelining and Vector Processing
Computer Organization Computer Architectures Lab
SISD  COMPUTER  SYSTEMS
Control
Unit
Processor
Unit
Memory
Instruction stream
Data stream
Characteristics
- Standard von Neumann machine
- Instructions and data are stored in memory
- One operation at a time
Limitations
Von Neumann bottleneck
Maximum speed of the system is limited by the
Memory Bandwidth (bits/sec or bytes/sec)
- Limitation on Memory Bandwidth
- Memory is shared by CPU and I/O
Parallel Processing