Pipeline Conflicts - Computer Organization and Architecture | EduRev Notes

Digital Electronics

Electronics and Communication Engineering (ECE) : Pipeline Conflicts - Computer Organization and Architecture | EduRev Notes

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Pipeline Conflicts

  • In general, there are three major difficulties that cause the instruction pipeline to deviate from its normal operation.
    • Resource conflicts caused by access to memory by two segments at the same time.
  •  Can be resolved by using separate instruction and data memories
    • Data dependency conflicts arise when an instruction depends on the result of a previous instruction, but this result is not yet available.
    • Branch difficulties arise from branch and other instructions that change the value of PC.
  • A difficulty that may cause a degradation of performance in an instruction pipeline is due to possible collision of data or address.
    • A data dependency occurs when an instruction needs data that are not yet available.
    • An address dependency may occur when an operand address cannot be calculated because the information needed by the addressing mode is not available.
  • Pipelined computers deal with such conflicts between data dependencies in a variety of ways.

Data Dependency Solutions 

  • Hardware interlocks:
    an interlock is a circuit that detects instructions whose source operands are destinations of instructions farther up in the pipeline.
    • This approach maintains the program sequence by using hardware to insert the required delays.
  • Operand forwarding:
    uses special hardware to detect a conflict and then avoid it by routing the data through special paths between pipeline segments.
    • This method requires additional hardware paths through multiplexers as well as the circuit that detects the conflict.
  • Delayed load: the compiler for such computers is designed to detect a data conflict and reorder the instructions as necessary to delay the loading of the conflicting data by inserting no-operation instructions.

Handling of Branch Instructions

  • One of the major problems in operating an instruction pipeline is the occurrence of branch instructions.
    • An unconditional branch always alters the sequential program flow by loading the program counter with the target address.
    • In a conditional branch, the control selects the target instruction if the condition is satisfied or the next sequential instruction if the condition is not satisfied.
  • Pipelined computers employ various hardware techniques to minimize the performance degradation caused by instruction branching.
  • Prefetch target instruction: To prefetch the target instruction in addition to the instruction following the branch. Both are saved until the branch is executed.
  • Branch target buffer(BTB): The BTB is an associative memory included in the fetch segment of the pipeline.
    • Each entry in the BTB consists of the address of a previously executed branch instruction and the target instruction for that branch.
    • It also stores the next few instructions after the branch target instruction
  • Loop buffer: This is a small very high speed register file maintained by the instruction fetch segment of the pipeline.  
  • Branch prediction: A pipeline with branch prediction uses some additional logic to guess the outcome of a conditional branch instruction before it is executed.
  • Delayed branch: in this procedure, the compiler detects the branch instructions and rearranges the machine language code sequence by inserting useful instructions that keep the pipeline operating without interruptions.
    • A procedure employed in most RISC processors.
    • e.g. no-operation instruction
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