Q1: Consider a digital display system (DDS) shown in the figure that displays the contents of register X. A 16-bit code word is used to load a word in X, either from S or from R. S is a 1024-word memory segment and R is a 32-word register file. Based on the value of mode bit M, T selects an input word to load in X. P and Q interface with the corresponding bits in the code word to choose the addressed word. Which one of the following represents the functionality of P, Q, and T? (2022)
(a) P is 10 : 1 multiplexer;
Q is 5 : 1 multiplexer;
T is 2 : 1 multiplexer
(b) P is 10 : 210 decoder;
Q is 5 : 25 decoder;
T is 2 : 1 encoder
(c) P is 10 : 210 decoder;
Q is 5 : 25 decoder;
T is 2 : 1 multiplexer
(d) P is 1 : 10 de-multiplexer;
Q is 1 : 5 de-multiplexer;
T is 2 : 1 multiplexer
Ans: (c)
Sol: If we observe, For T, there is select line, input and output lines shown in the diagram.
There are no select lines associated with P and Q ( only input and output lines shown in diagram )
Therefore P and Q are neither Multiplexers nor De-Multiplexers.
Those can be Decoders and T is Multiplexer of size 2 x 1
Option C is correct.
Q2: Micro program is: (2018)
(a) the name of a source program in micro computers
(b) set of microinstructions that defines the individual operations in response to a machine-language instruction
(c) a primitive form of macros used in assembly language programming
(d) a very small segment of machine code
Ans: (b)
Q3: Consider a main memory system that consists of 8 memory modules attached to the system bus, which is one word wide. When a write request is made, the bus is occupied for 100 nanoseconds (ns) by the data, address, and control signals. During the same 100 ns, and for 500 ns thereafter, the addressed memory module executes one cycle accepting and storing the data. The (internal) operation of different memory modules may overlap in time, but only one request can be on the bus at any time. The maximum number of stores (of one word each) that can be initiated in 1 millisecond is ____________ (2014 SET-2)
(a) 5000
(b) 10000
(c) 2000
(d) 8000
Ans: (b)
Sol: When a write request is made, the bus is occupied for 100 ns. So, between 2 writes at least 100 ns interval must be there.
Now, after a write request, for 100+500 = 600 ns, the corresponding memory module is busy storing the data. But, assuming the next stores are to a different memory module (we have totally 8 modules in question), we can have consecutive stores at intervals of 100 ns. So, maximum number of stores in 1 ms.
= 10-3 x 1/(100 x 10-9) = 10,000
Q4: Two control signals in microprocessor which are related to Direct Memory Access (DMA) are (2011)
(a) INTR & INTA
(b) RD & WR
(c) S0 & S1
(d) HOLD & HLDA
Ans: (d)
Sol: The DMA Controller sends a Hold request line to the CPU and waits for the CPU to assert the HLDA.
Q5: The microinstructions stored in the control memory of a processor have a width of 26 bits. Each microinstruction is divided into three fields. a micro operation field of 13 bits, a next address field (X), and a MUX select field (Y). There are 8 status bits in the inputs of the MUX. How many bits are there in the X and Y fields, and what is the size of the control memory in number of words? (2009)
(a) 10, 3, 1024
(b) 8, 5, 256
(c) 5, 8, 2048
(d) 10, 3, 512
Ans: (a)
Sol: MUX has 8 states bits as input lines so we require 3 select inputs to select and input lines.
No. of bits in control memory next address field = 26 - 13 - 3 = 10
10 bit addressing .we have 2^10=1024 memory size
So X, Y size = 10, 3
So (A) is correct option.
Q6: Consider a CPU where all the instructions require 7 clock cycles to complete execution. There are 140 instructions in the instruction set. It is found that 125 control signals are needed to be generated by the control unit. While designing the horizontal microprogrammed control unit, single address field format is used for branch control logic. What is the minimum size of the control word and control address register? (2008)
(a) 125, 7
(b) 125, 10
(c) 135, 9
(d) 135, 10
Ans: (d)
Sol: Its answer should be (D) because 140 instructions, each requiring 7 cycles means 980 cycles which will take 10 bits.
Since it is horizontal for control word, 125 control signals +10 bits = 135 bits will be required.
Q7: The data path shown in the figure computes the number of 1s in the 32-bit input word corresponding to an unsigned even integer stored in the shift register.
The unsigned counter, initially zero, is incremented if the most significant bit of the shift register is 1.
The microprogram for the control is shown in the table below with missing control words for microinstructions I1, I2,…In.
The counter width (k), the number of missing microinstructions (n), and the control word for microinstructions I1, I2,…In are, respectively, (2006)
(a) 32, 5, 010
(b) 5, 32, 010
(c) 5, 31, 011
(d) 5, 31, 010
Ans: (d)
Sol: Answer I1 to In are microinstructions and reset_counter, shift_left and load_output are control signals to activate corresponding hardware(eg. Shift register or load output).
Counter width (k) is 5 bits as shift register uses 32 bit data Only.
The number of missing micro instructions (n) should be 31 as shift register contain Only unsigned EVEN integer. LSB Will be always 0 so no need to shift for LSB.
Control word contains:-
1 for active/enable. 0 for inactive or disabled.
Reset counter is to reset the counter so it must be 0 for all microns.
Shift_left CS should be 1 to shift the given data in shift reg.
And load output has no meaning to make output active for all microinstructions as it will be used in the END only so it should be 0.
The microprogram for the control is shown in the table below with missing control words for microinstructions I1, I2,…In.
The counter width (k), the number of missing microinstructions (n), and the control word for microinstructions I1, I2,…In are, respectively, (2006)
