Previous Year Questions: IO Interface | Computer Architecture & Organisation (CAO) - Computer Science Engineering (CSE) PDF Download

Q1: Consider a computer with a 4 MHz processor. Its DMA controller can transfer 8 bytes in 1 cycle from a device to main memory through cycle stealing at regular intervals. Which one of the following is the data transfer rate (in bits per second) of the DMA controller if 1% of the processor cycles are used for DMA?  (2024 SET-2 )
(a) 2,56,000
(b) 3,200
(c) 25,60,000
(d) 32,000
Ans: (c)
Sol: Cycle time = 1/4MHZ = 0.25us
Transfer time = ty = 1 cycle = 0.25 us
Cycle stealing mode (given)
% cpu block = (ty/tx)*100
1 = ty/tx *100
tx = ty*100
tx = 25us
In 25 us 8B data is transferred
In 25us 8*8 bits data is transferred
In 1 sec  64/25us data is transferred
So data transfer rate = 64/25us
= 2.56*10⁶
So answer is option C.

Q2: Which one of the following statements is FALSE?  (2024 SET-1)
(a) In the cycle stealing mode of DMA, one word of data is transferred between an I/O device and main memory in a stolen cycle
(b) For bulk data transfer, the burst mode of DMA has a higher throughput than the cycle stealing mode
(c) Programmed I/O mechanism has a better CPU utilization than the interrupt driven I/O mechanism
(d) The CPU can start executing an interrupt service routine faster with vectored interrupts than with non-vectored interrupts
Ans: (c)
Sol: (Programmed i/o is like polling(can remeber to recall the concept) so to check wether there is i/o who need's cpu ,cpu has to do alot of work, but in interrupt driven i/o ,i/o has given preveleged to tell cpu that i need you by sending the interrupt so cpu in is more utilized in interrupt driven i/o)

Q3: Which one of the following facilitates transfer of bulk data from hard disk to main memory with the highest throughput?  (2022)
(a) DMA based I/O transfer
(b) Interrupt driven I/O transfer
(c) Polling based I/O transfer
(d) Programmed I/O transfer
Ans: (a)
Sol: DMA(Direct memory access) is used for transferring bulk data from Main Memory with the highest throughput as the CPU is unable to access the hard disk directly.
DMA helps in the effective utilization of the CPU’s time.
Another method used for data transfer in a similar fashion is programmed Input/Output but this method is quite slow.

Q4: Consider a computer system with DMA support. The DMA module is transferring one 8-bit character in one CPU cycle from a device to memory through cycle stealing at regular intervals. Consider a 2 MHz processor. If 0.5% processor cycles are used for DMA, the data transfer rate of the device is __________ bits per second.  (2021 SET-2)
(a) 10000
(b) 80000
(c) 40000
(d) 20000
Ans: (b)
Sol: To complete one cycle at 2 MHz it will take 1/2x10⁶ seconds. So the total number of CPU cycles in one second will be 2 × 10⁶.
Now 0.5% of these cycles are taken by DMA to transfer the data.
So total number of cycles taken to transfer the data will be (0.5/100) x 2 x 10⁶ = 10,000 and in each cycle 8 bits are transferred.
So, data transfer rate in bits per second = 8 × 10000 = 80,000.  

Q5: Of the following, which best characterizes computers that use memory-mapped I/O?  (2018)
(a) The computer provides special instructions for manipulating I/O ports
(b) I/O ports are placed at addresses on the bus and are accessed just like other memory locations
(c) To perform I/O operations. it is sufficient to place the data in an address register and call channel to perform the operation
(d) I/O can be performed only when memory management hardware is turned on
Ans: (b)
Sol: In memory some of the address of the Memory are assigned to IO port. so whenever those address are placed we refer to the IO devices.
option B.

Q6: The size of the data count register of a DMA controller is 16 bits.The processor needs to transfer a file of 29,154 kilobytes from disk to main memory.The memory is byte addressable. The minimum number of times the DMA control lerneeds to get the control of the systembus from the processor to transfer the file from the disk to main memory is ____.  (2016 SET-1)
(a) 1
(b) 456
(c) 228
(d) 114
Ans: (b)
Sol: Data count register gives the number of words the DMA can transfer in a single cycle.
Here it is 16 bits.. so max 2¹⁶ words can be transferred in one cycle..
Since memory is byte addressable.. 1 word = 1byte
so 2¹⁶ bytes in 1 cycle.
Now for the given file..
File size = 29154 KB = 29154 × 2¹⁰ B
1 cylce → DMA transfers 2¹⁶ B
i.e
1 B transfered by DMA → (1/2¹⁶) cycles.
Now, for full file of size 29154 KB,
Minimum number of cylces = But number of cylces is asked so  455.53 → 456.

Q7: A processor is fetching instructions at the rate of 1 MIPS. A DMA module is used to transfer characters to RAM from a device transmitting at 9600 bps. How much time will the processor be slowed down due to DMA activity?  (2013)
(a) 9.6ms
(b) 4.8ms
(c) 2.4ms
(d) 1.2ms
Ans: (d)
Sol:  External Device sends data to DMA module in 1 sec = 9600 bits
= 9600/8 = 1200 Bytes
Now Processor runs instructions in 1 second= 1 Million  (because 1 MIPS means 1 million instructions per second)
= 10⁶
So time will the processor be slowed down due to DMA activity =  1200 / (10⁶) = 0.0012 seconds
= 1.2 ms.

Q8: In DMA transfer scheme, the transfer scheme other than burst mode is  (2011)
(a) cycle technique
(b) stealing technique
(c) cycle stealing technique
(d) cycle bypass technique
Ans: (c)
Sol: (1) Cycle Steal:
A read or write signal is generated by the DMAC, and the I/O device either generates or latches the data. The DMAC effectively steals cycles from the processor in order to transfer the byte, so single byte transfer is also known as cycle stealing.
(2) Burst Transfer:
To achieve block transfers, some DMAC's incorporate an automatic sequencing of the value presented on the address bus. A register is used as a byte count, being decremented for each byte transfer, and upon the byte count reaching zero, the DMAC will release the bus. When the DMAC operates in burst mode, the CPU is halted for the duration of the data transfer.
(3) Hidden DMA:
It is possible to perform hidden DMA, which is transparent to the normal operation of the CPU. In other words, the bus is grabbed by the DMAC when the processor is not using it. The DMAC monitors the execution of the processor, and when it recognises the processor executing an instruction which has sufficient empty clock cycles to perform a byte transfer, it waits till the processor is decoding the op code, then grabs the bus during this time.  The processor is not slowed down, but continues processing normally. Naturally, the data transfer by the DMAC must be completed before the processor starts.

Q9: On a non-pipelined sequential processor, a program segment, which is a part of the interrupt service routine, is given to transfer 500 bytes from an I/O device to memory.
Initialize the address register
Initialize the count to 500
LOOP: Load a byte from device
Store in memory at address given by address register
Increment the address register
Decrement the count
If count != 0 go to LOOP
Assume that each statement in this program is equivalent to a machine instruction which takes one clock cycle to execute if it is a non-load/store instruction. The load-store instructions take two clock cycles to execute.
The designer of the system also has an alternate approach of using the DMA controller to implement the same transfer. The DMA controller requires 20 clock cycles for initialization and other overheads. Each DMA transfer cycle takes two clock cycles to transfer one byte of data from the device to the memory.
What is the approximate speedup when the DMA controller based design is used in place of the interrupt driven program based input-output?  (2011)
(a) 3.4
(b) 4.4
(c) 5.1
(d) 6.7
Ans: (a)
Sol: Interrupt driven transfer time = 1 + 1 + 500 × (2 + 2 + 1 + 1 + 1) = 3502
DMA based transfer time = 20 + 500 × 2 = 1020
Speedup = 3502/1020 = 3.4
Correct Answer: A