The document Propagation Delay Calculation of CMOS Inverter - Electronics & Communication Engineering Electrical Engineering (EE) Notes | EduRev is a part of the Electrical Engineering (EE) Course VLSI System Design.

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**Objectives**

In this lecture you will learn the following

- Few Definitions
- Quick Estimates
- Rise and Fall times Calculation

**16.1 Few Definitions**

Before calculating the propagation delay of CMOS Inverter, we will define some basic terms-

**Switching speed -**limited by time taken to charge and discharge, C_{L}.**Rise time, t**waveform to rise from 10% to 90% of its steady state value_{r}:**Fall time**90% to 10% of steady state value**t**, :_{f}**Delay time,****t**_{d}**:**time difference between input transition (50%) and 50% output level

The propagation delay **t**_{p} of a gate defines how quickly it responds to a change at its inputs, it expresses the delay experienced by a signal when passing through a gate. It is measured between the 50% transition points of the input and output waveforms as shown in the figure 16.1 for an inverting gate. The defines the response time of the gate for a low to high output transition, while refers to a high to low transition. The propagation delay as the average of the two

**16.2 Quick Estimates:**

We will give an example of how to calculate quick estimate. From ffig 16.22, we can write following equations..

**Fig 16.21: Example CMOS Inverter Circuit**

From figure 16.21, when Vin = 0 the capacitor CL charges through the P-MOS, and when Vin = 5 the capacitor discharges through the N-MOS

**Fig 16.22 : Propagation Delay of above**

The capacitor current is - **MOS Circuit**

From this the delay times can be derived as

The expressions for the propagation delays as denoted in the figure (16.22) can be easily seen to be

**16.3 Rise and Fall Times**

Figure 16.21 shows the familiar CMOS inverter with a capacity load C_{L }that represents the load capacitance (input of next gates, output of this gate and routing). Of interest is the voltage waveform V** _{out}(t)** when the input is driven by a step waveform, V

Figure 16.31 shows the trajectory of the n-transistor operating point as the input voltage, V**in(t)**, changes from 0V to V**DD**. Initially, the end-device is cutt-off and the load capacitor is charged to V**DD**. This illustrated by X**1** on the characteristic curve. Application of a step voltage (V**GS** = V**DD**) at the input of the inverter changes the operating point to X**2**. From there onwards the trajectory moves on the V**GS** = V**DD** characteristic curve towards point X**3** at the origin.

**Fig 16.31: trjectory of n-transistor operating point**

Thus it is evident that the fall time consists of two intervals;

1.t_{f1}=period during which the capacitor voltage, V_{out}, drops from 0.9V_{DD} to (V_{DD}â€“ V_{tn})

2. t_{f2}=period during which the capacitor voltage, V_{out}, drops from **(V _{DD} â€“ V_{tn} )** to 0.1V

The equivalent circuits that illustrate the above behavior are show in figure (16.32 & 16.33 ).

**Figure 16.32: Equivalent circuit for showing behav. of t _{f1} Figure 16.33: Equivalent circuit for showing behav. of t_{f2}**

As we saw in last section, the delay periods can be derived using the general equation

From figure (16.32) while in saturation,

**Fig 16.34: Rise and Fall time graph**

Integrating from t = t_{1,} corresponding to V_{out}=0.9 V_{DD}, to t = t_{2 }corresponding to V_{out}**=(V _{DD}-V_{tn}) results in,**

When the n-device begins to operate in the linear region, the

discharge current is no longer constant. The time t_{f1} taken to discharge the capacitor voltage from **(V _{DD}-V_{tn})** to

Thus the complete term for the fall time is,

The fall time tf can be approximated as,

From this expression we can see that the delay is directly proportional to the load capacitance. Thus to achieve high speed circuits one has to minimize the load capacitance seen by a gate. Secondly it is inversely proportion to the supply voltage i.e. as the supply voltage is raised the delay time is reduced. Finally, the delay is proportional to the Î²**n** of the driving transistor so increasing the width of a transistor decreases the delay.

Due to the symmetry of the CMOS circuit the rise time can be similarly obtained as;

For equally sized **n** and **p** transistors (where Î²** _{n}=2Î²_{p}**) t

Thus the fall time is faster than the rise time primarily due to different carrier mobilites associated with the p and n devices thus if we want t_{f}=t_{r} we need to make Î²_{n}/**Î² _{p} **=

The propagation delays if calculated as indicated before turn out to be,

**Figure 16.35: Rise and Fall time graph of Output w.r.t Input**

If we consider the rise time and fall time of the input signal as well, as shown in the fig 16.35 we have,

These are the rms values for the propagation delays.

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35 docs|28 tests

### Pseudo NMOS Inverter (Part - 1)

- Doc | 2 pages
### Pseudo NMOS Inverter (Part - 2)

- Doc | 1 pages
### Pseudo NMOS Inverter (Part - 3)

- Doc | 1 pages
### Analyzing Delay for Various Logic Circuits

- Doc | 5 pages
### Analyzing Delay in few Sequential Circuits

- Doc | 5 pages

- CMOS Inverter Characteristics
- Doc | 4 pages
- Test: Propagation Delays
- Test | 10 ques | 10 min